fix minu[.] to be unsigned

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index fd5424c8e27a462080bb61ab76f5abfcc56aad0d..91ef617da295d40ea39530285b91446bb0210e96 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -59,8 +59,8 @@ X-Form
 
 Pseudo-code:
 
-    if   (RA) < (RB) then RT <- (RA)
-    else                  RT <- (RB)
+    if   (RA) <u (RB) then RT <- (RA)
+    else                   RT <- (RB)
 
 Special Registers Altered:
 

diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 6e689e9fd889a69f8af90aa4b79f987a517b5ae2..a77b52024bd1cf3140220c53abd27247a660ef9c 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -165,8 +165,8 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 1
         e.intregs[2] = 0x8000_0000_0000_0000
-        e.intregs[3] = 0x8000_0000_0000_0000
-        e.crregs[0] = 0x8 # RT is -ve
+        e.intregs[3] = min(e.intregs[1], e.intregs[2])
+        e.crregs[0] = 0x4
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_avgadd(self):