Use soft-logic, not LUT3 instantiation

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 2c88e0141df7612d3e62ef7da7c6b402a6f87128..4173814fde90de5a07804418addc20097b367fb1 100644 (file)
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -134,10 +134,8 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       else begin
         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
-        // FIXME: Need to instantiate 2:1 MUX here since
-        //        techmap with this file is run AFTER abc
-        //assign Q = L[lower_clog2-1] ? T2 : T0;
-        LUT3 #(.INIT(8'b10101100)) fpga_mux (.I0(T2), .I1(T0), .I2(L[lower_clog2]), .O(Q));
+        wire [1023:0] _TECHMAP_DO_ = "techmap -map +/techmap.v";
+        assign Q = L[lower_clog2] ? T2 : T0;
       end
       if (DEPTH == 2 * lower_depth)
           assign SO = T3;