midgard_op_ld_vary_32i = 0x9B,
/* Old version of midgard_op_ld_color_buffer_as_fp16, for T720 */
+ midgard_op_ld_color_buffer_as_fp32_old = 0x9C,
midgard_op_ld_color_buffer_as_fp16_old = 0x9D,
midgard_op_ld_color_buffer_32u_old = 0x9E,
midgard_op_ld_ubo_int4 = 0xB0,
/* New-style blending ops. Works on T760/T860 */
+ midgard_op_ld_color_buffer_as_fp32 = 0xB8,
midgard_op_ld_color_buffer_as_fp16 = 0xB9,
midgard_op_ld_color_buffer_32u = 0xBA,
M_STORE(st_int4, nir_type_uint32);
M_LOAD(ld_color_buffer_32u, nir_type_uint32);
M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
+M_LOAD(ld_color_buffer_as_fp32, nir_type_float32);
M_STORE(st_vary_32, nir_type_uint32);
M_LOAD(ld_cubemap_coords, nir_type_uint32);
M_LOAD(ld_compute_id, nir_type_uint32);
case nir_intrinsic_load_output: {
reg = nir_dest_index(&instr->dest);
- midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
+ unsigned bits = nir_dest_bit_size(instr->dest);
+
+ midgard_instruction ld;
+ if (bits == 16)
+ ld = m_ld_color_buffer_as_fp16(reg, 0);
+ else
+ ld = m_ld_color_buffer_as_fp32(reg, 0);
ld.load_store.arg_2 = output_load_rt_addr(ctx->nir, instr);
ld.swizzle[0][c] = 0;
if (ctx->quirks & MIDGARD_OLD_BLEND) {
- ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
+ if (bits == 16)
+ ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
+ else
+ ld.load_store.op = midgard_op_ld_color_buffer_as_fp32_old;
ld.load_store.address = 1;
ld.load_store.arg_2 = 0x1E;
}
[midgard_op_ld_color_buffer_32u] = {"ld_color_buffer_32u", M32},
[midgard_op_ld_color_buffer_32u_old] = {"ld_color_buffer_32u_old", M32},
[midgard_op_ld_color_buffer_as_fp16] = {"ld_color_buffer_as_fp16", M16},
+ [midgard_op_ld_color_buffer_as_fp32] = {"ld_color_buffer_as_fp32", M32},
[midgard_op_ld_color_buffer_as_fp16_old] = {"ld_color_buffer_as_fp16_old", M16 | LDST_SPECIAL_MASK},
+ [midgard_op_ld_color_buffer_as_fp32_old] = {"ld_color_buffer_as_fp32_old", M32 | LDST_SPECIAL_MASK},
[midgard_op_ld_ubo_char] = {"ld_ubo_char", M32},
[midgard_op_ld_ubo_char2] = {"ld_ubo_char2", M16},