migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)

diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index cd4360729230b0fe5390434ff22e28a8719a9ab4..ab8cc9bf50f95135a3b7dde805fb489f6df77fa4 100644 (file)
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -35,7 +35,7 @@ class DifferentialOutput(Special):
                raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
 
 class CRG(Module):
-       def __init__(self, clk, rst=Signal()):
+       def __init__(self, clk, rst=0):
                self.clock_domains.cd_sys = ClockDomain()
                self.clock_domains.cd_por = ClockDomain(reset_less=True)