fhdl: support inverted clock ports in instances

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 6b77840b30d1fe96461aa925ac2df0dda4f7e756..27d7bdcb989d9300a5cf43c4295a0b0dab9c9e7c 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -274,9 +274,10 @@ class Instance:
                        self.value = value
        
        class _CR:
-               def __init__(self, name_inst, domain="sys"):
+               def __init__(self, name_inst, domain="sys", invert=False):
                        self.name_inst = name_inst
                        self.domain = domain
+                       self.invert = invert
        class ClockPort(_CR):
                pass
        class ResetPort(_CR):

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d0cbecf8f9dc64c50f9d5c07f6b48d17d3595355..e48875f78180f36a444c221bd031692996e79e61 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -210,6 +210,8 @@ def _printinstances(f, ns, clock_domains):
                        elif isinstance(p, Instance.ClockPort):
                                name_inst = p.name_inst
                                name_design = ns.get_name(clock_domains[p.domain].clk)
+                               if p.invert:
+                                       name_design = "~" + name_design
                        elif isinstance(p, Instance.ResetPort):
                                name_inst = p.name_inst
                                name_design = ns.get_name(clock_domains[p.domain].rst)