Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 3e342453dec1128bb50966d062d7ed185efdb7fc..3a054a4632bc6966d6c40bde5328ba6797980c13 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -91,8 +91,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setPort("\\C", CD.extract(0, 16));
        cell->setPort("\\D", CD.extract(16, 16));
 
-       cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1);
-       cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1);
+       cell->setParam("\\A_REG", pm.st.ffA ? State::S1 : State::S0);
+       cell->setParam("\\B_REG", pm.st.ffB ? State::S1 : State::S0);
 
        cell->setPort("\\AHOLD", State::S0);
        cell->setPort("\\BHOLD", State::S0);

diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 300ce9aa6c10bd146f1101f836dc5abc27a5244e..120286550c56016b1418fe45c388fc90452a07e2 100644 (file)
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -5,6 +5,7 @@
 /test_dsp_model_ref.v
 /test_dsp_model_uut.v
 /test_dsp_map
+/test_dsp_map.vcd
 /test_dsp_map_tb.v
 /test_dsp_map_top.v
 /test_dsp_map_syn.v

diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
index 5982e5b34cc3b3a4f10c3bbd71be48b0a98e1ad9..3f7f134e4c3916b0714f5fb54754439eecea39a4 100644 (file)
--- a/techlibs/ice40/tests/test_dsp_map.sh
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -1,26 +1,28 @@
 #!/bin/bash
 set -ex
 
-SZA=$(( 3 + $RANDOM % 13 ))
-SZB=$(( 3 + $RANDOM % 13 ))
-SZO=$(( 3 + $RANDOM % 29 ))
+for iter in {1..100}
+do
+       SZA=$(( 3 + $RANDOM % 13 ))
+       SZB=$(( 3 + $RANDOM % 13 ))
+       SZO=$(( 3 + $RANDOM % 29 ))
 
-C0=clk$(( $RANDOM & 1))
-C1=clk$(( $RANDOM & 1))
-C2=clk$(( $RANDOM & 1))
-C3=clk$(( $RANDOM & 1))
+       C0=clk$(( $RANDOM & 1))
+       C1=clk$(( $RANDOM & 1))
+       C2=clk$(( $RANDOM & 1))
+       C3=clk$(( $RANDOM & 1))
 
-E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+       E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+       E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+       E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+       E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
 
-SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+       SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
 
-RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
-RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+       RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+       RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
 
-cat > test_dsp_map_top.v << EOT
+       cat > test_dsp_map_top.v << EOT
 module top (
        input clk0, clk1, reset,
        input  [$SZA:0] A,
@@ -38,7 +40,7 @@ module top (
 endmodule
 EOT
 
-cat > test_dsp_map_tb.v << EOT
+       cat > test_dsp_map_tb.v << EOT
 \`timescale 1ns / 1ps
 module testbench;
        reg clk1, clk0, reset;
@@ -51,10 +53,14 @@ module testbench;
        syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
 
        initial begin
+               // \$dumpfile("test_dsp_map.vcd");
+               // \$dumpvars(0, testbench);
+
                #2;
                clk0 = 0;
                clk1 = 0;
                reset = 1;
+               reset = $RC;
                A = 0;
                B = 0;
 
@@ -82,14 +88,20 @@ module testbench;
                                \$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
                                \$stop;
                        end
-                       \$display("OK O_top=O_syn=%b", O_top);
+                       // \$display("OK O_top=O_syn=%b", O_top);
                end
 
+               \$display("Test passed.");
                \$finish;
        end
 endmodule
 EOT
 
-../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
-iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
-vvp -N test_dsp_map
+       ../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+       iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+       vvp -N test_dsp_map
+done
+
+: ""
+: "####  All tests passed.  ####"
+: ""