split out instructions from openpower/isa/condition.mdwn

diff --git a/openpower/isa/condition.mdwn b/openpower/isa/condition.mdwn
index 5cef0675a2d997d22f3119adf7e799c742ff791d..f675ff807f305b50ec88d81ed80e2d8effdac6de 100644 (file)
--- a/openpower/isa/condition.mdwn
+++ b/openpower/isa/condition.mdwn
@@ -10,130 +10,20 @@
 <!-- * The bit specified by BT is in the same Condition Register field as the bit -->
 <!-- specified by BB. -->
 
-# Condition Register AND
+[[!inline pagenames="openpower/isa/condition/crand" raw="yes"]]
 
-XL-Form
+[[!inline pagenames="openpower/isa/condition/crnand" raw="yes"]]
 
-* crand BT,BA,BB
+[[!inline pagenames="openpower/isa/condition/cror" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/condition/crxor" raw="yes"]]
 
-    CR[BT+32] <-  CR[BA+32] & CR[BB+32]
+[[!inline pagenames="openpower/isa/condition/crnor" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/condition/creqv" raw="yes"]]
 
-    CR[BT+32]
+[[!inline pagenames="openpower/isa/condition/crandc" raw="yes"]]
 
-# Condition Register NAND
+[[!inline pagenames="openpower/isa/condition/crorc" raw="yes"]]
 
-XL-Form
-
-* crnand BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register OR
-
-XL-Form
-
-* cror BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <-  CR[BA+32] | CR[BB+32]
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register XOR
-
-XL-Form
-
-* crxor     BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register NOR
-
-XL-Form
-
-* crnor BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register Equivalent
-
-XL-Form
-
-* creqv BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register AND with Complement
-
-XL-Form
-
-* crandc BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- CR[BA+32] &  ¬CR[BB+32]
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Condition Register OR with Complement
-
-XL-Form
-
-* crorc BT,BA,BB
-
-Pseudo-code:
-
-    CR[BT+32] <- CR[BA+32] |  ¬CR[BB+32]
-
-Special Registers Altered:
-
-    CR[BT+32]
-
-# Move Condition Register Field
-
-XL-Form
-
-* mcrf BF,BFA
-
-Pseudo-code:
-
-    CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
-
-Special Registers Altered:
-
-    CR field BF
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/condition/mcrf" raw="yes"]]

diff --git a/openpower/isa/condition/crand.mdwn b/openpower/isa/condition/crand.mdwn
new file mode 100644 (file)
index 0000000..f779bc3
--- /dev/null
+++ b/openpower/isa/condition/crand.mdwn
@@ -0,0 +1,13 @@
+# Condition Register AND
+
+XL-Form
+
+* crand BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crand_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crand_code.mdwn b/openpower/isa/condition/crand_code.mdwn
new file mode 100644 (file)
index 0000000..0679ba5
--- /dev/null
+++ b/openpower/isa/condition/crand_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <-  CR[BA+32] & CR[BB+32]

diff --git a/openpower/isa/condition/crandc.mdwn b/openpower/isa/condition/crandc.mdwn
new file mode 100644 (file)
index 0000000..68332fa
--- /dev/null
+++ b/openpower/isa/condition/crandc.mdwn
@@ -0,0 +1,13 @@
+# Condition Register AND with Complement
+
+XL-Form
+
+* crandc BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crandc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crandc_code.mdwn b/openpower/isa/condition/crandc_code.mdwn
new file mode 100644 (file)
index 0000000..2de6dca
--- /dev/null
+++ b/openpower/isa/condition/crandc_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- CR[BA+32] &  ¬CR[BB+32]

diff --git a/openpower/isa/condition/creqv.mdwn b/openpower/isa/condition/creqv.mdwn
new file mode 100644 (file)
index 0000000..31e9f1a
--- /dev/null
+++ b/openpower/isa/condition/creqv.mdwn
@@ -0,0 +1,13 @@
+# Condition Register Equivalent
+
+XL-Form
+
+* creqv BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/creqv_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/creqv_code.mdwn b/openpower/isa/condition/creqv_code.mdwn
new file mode 100644 (file)
index 0000000..74d16dd
--- /dev/null
+++ b/openpower/isa/condition/creqv_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])

diff --git a/openpower/isa/condition/crnand.mdwn b/openpower/isa/condition/crnand.mdwn
new file mode 100644 (file)
index 0000000..e011936
--- /dev/null
+++ b/openpower/isa/condition/crnand.mdwn
@@ -0,0 +1,13 @@
+# Condition Register NAND
+
+XL-Form
+
+* crnand BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crnand_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crnand_code.mdwn b/openpower/isa/condition/crnand_code.mdwn
new file mode 100644 (file)
index 0000000..5e193fc
--- /dev/null
+++ b/openpower/isa/condition/crnand_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])

diff --git a/openpower/isa/condition/crnor.mdwn b/openpower/isa/condition/crnor.mdwn
new file mode 100644 (file)
index 0000000..cbb1ac1
--- /dev/null
+++ b/openpower/isa/condition/crnor.mdwn
@@ -0,0 +1,13 @@
+# Condition Register NOR
+
+XL-Form
+
+* crnor BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crnor_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crnor_code.mdwn b/openpower/isa/condition/crnor_code.mdwn
new file mode 100644 (file)
index 0000000..f623620
--- /dev/null
+++ b/openpower/isa/condition/crnor_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])

diff --git a/openpower/isa/condition/cror.mdwn b/openpower/isa/condition/cror.mdwn
new file mode 100644 (file)
index 0000000..2e08673
--- /dev/null
+++ b/openpower/isa/condition/cror.mdwn
@@ -0,0 +1,13 @@
+# Condition Register OR
+
+XL-Form
+
+* cror BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/cror_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/cror_code.mdwn b/openpower/isa/condition/cror_code.mdwn
new file mode 100644 (file)
index 0000000..7630182
--- /dev/null
+++ b/openpower/isa/condition/cror_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <-  CR[BA+32] | CR[BB+32]

diff --git a/openpower/isa/condition/crorc.mdwn b/openpower/isa/condition/crorc.mdwn
new file mode 100644 (file)
index 0000000..6eba125
--- /dev/null
+++ b/openpower/isa/condition/crorc.mdwn
@@ -0,0 +1,13 @@
+# Condition Register OR with Complement
+
+XL-Form
+
+* crorc BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crorc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crorc_code.mdwn b/openpower/isa/condition/crorc_code.mdwn
new file mode 100644 (file)
index 0000000..36ee7de
--- /dev/null
+++ b/openpower/isa/condition/crorc_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- CR[BA+32] |  ¬CR[BB+32]

diff --git a/openpower/isa/condition/crxor.mdwn b/openpower/isa/condition/crxor.mdwn
new file mode 100644 (file)
index 0000000..549608b
--- /dev/null
+++ b/openpower/isa/condition/crxor.mdwn
@@ -0,0 +1,13 @@
+# Condition Register XOR
+
+XL-Form
+
+* crxor     BT,BA,BB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/crxor_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR[BT+32]

diff --git a/openpower/isa/condition/crxor_code.mdwn b/openpower/isa/condition/crxor_code.mdwn
new file mode 100644 (file)
index 0000000..7c6bdb3
--- /dev/null
+++ b/openpower/isa/condition/crxor_code.mdwn
@@ -0,0 +1 @@
+    CR[BT+32] <- CR[BA+32] ^ CR[BB+32]

diff --git a/openpower/isa/condition/mcrf.mdwn b/openpower/isa/condition/mcrf.mdwn
new file mode 100644 (file)
index 0000000..53b14a9
--- /dev/null
+++ b/openpower/isa/condition/mcrf.mdwn
@@ -0,0 +1,15 @@
+# Move Condition Register Field
+
+XL-Form
+
+* mcrf BF,BFA
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/condition/mcrf_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR field BF
+
+<!-- Checked March 2021 -->

diff --git a/openpower/isa/condition/mcrf_code.mdwn b/openpower/isa/condition/mcrf_code.mdwn
new file mode 100644 (file)
index 0000000..ef291b5
--- /dev/null
+++ b/openpower/isa/condition/mcrf_code.mdwn
@@ -0,0 +1 @@
+    CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]