r600g: set full register mask for CB_COLOR_CONTROL on evergreen

We don't set the other bits anywhere else.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 57942fb0bc91bf1b0b6aedfee3c67b44d2cafaf8..7fd3a368bf7ad2947cd28f1922be167e660c39ba 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -750,7 +750,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
        blend->cb_target_mask = target_mask;
        
        r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
-                               color_control, 0xFFFFFFFD, NULL, 0);
+                               color_control, 0xFFFFFFFF, NULL, 0);
 
        if (rctx->chip_class != CAYMAN)
                r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);