unsigned family;
enum chip_class chip_class;
boolean use_mem_constant; /* true for evergreen */
+ struct pb_manager *mman; /* malloc manager */
+ struct pb_manager *kman; /* kernel bo manager */
+ struct pb_manager *cman; /* cached bo manager */
};
struct radeon *r600_new(int fd, unsigned device);
struct radeon_bo *src);
unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo);
-
+void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr);
static int r600_group_id_register_offset(struct r600_context *ctx, unsigned offset)
{
/* suspend queries */
r600_context_queries_suspend(ctx);
+ radeon_bo_pbmgr_flush_maps(ctx->radeon->kman);
#if 1
/* emit cs */
drmib.num_chunks = 2;
unsigned family;
enum chip_class chip_class;
boolean use_mem_constant; /* true for evergreen */
- unsigned nstype;
- struct radeon_stype_info *stype;
- unsigned max_states;
struct pb_manager *mman; /* malloc manager */
struct pb_manager *kman; /* kernel bo manager */
struct pb_manager *cman; /* cached bo manager */
+ unsigned nstype;
+ struct radeon_stype_info *stype;
+ unsigned max_states;
};
struct radeon_ws_bo {