interconnect/stream: set default AsyncFIFO depth to None and add depth parameter...

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 5f5bd540258072615d82d255f9e09d031e0fe506..86d9c375f48901d305ae1700fd5c7ca5325766c7 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -228,7 +228,8 @@ class SyncFIFO(_FIFOWrapper):
 
 
 class AsyncFIFO(_FIFOWrapper):
-    def __init__(self, layout, depth=4, buffered=False):
+    def __init__(self, layout, depth=None, buffered=False):
+        depth = 4 if depth is None else depth
         assert depth >= 4
         _FIFOWrapper.__init__(self,
             fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
@@ -238,7 +239,7 @@ class AsyncFIFO(_FIFOWrapper):
 # ClockDomainCrossing ------------------------------------------------------------------------------
 
 class ClockDomainCrossing(Module):
-    def __init__(self, layout, cd_from="sys", cd_to="sys"):
+    def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None):
         self.sink   = Endpoint(layout)
         self.source = Endpoint(layout)
         # # #
@@ -246,7 +247,7 @@ class ClockDomainCrossing(Module):
         if cd_from == cd_to:
             self.comb += self.sink.connect(self.source)
         else:
-            cdc = AsyncFIFO(layout)
+            cdc = AsyncFIFO(layout, depth)
             cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
             self.submodules += cdc
             self.comb += self.sink.connect(cdc.sink)