Fix handling of v850e bit-twiddle instructions.

	* simops.c (OP_E6077E0): And op1 with 7 after reading register, not
	before.
	(BIT_CHANGE_OP): Likewise.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 100ece186e5879c2db49184e8f7a6cd819524361..2053096ece54d9cf75960014cf399315c077d5a4 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,9 @@
+2002-09-27  Jim Wilson  <wilson@redhat.com>
+
+       * simops.c (OP_E6077E0): And op1 with 7 after reading register, not
+       before.
+       (BIT_CHANGE_OP): Likewise.
+
 2002-09-26  Jim Wilson  <wilson@redhat.com>
 
        * simops (OP_10007E0): Don't subtract 4 from PC.

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index eba728fa287cdd88ee98d270ac62ae24aa8d8744..04045234629fe78e1b3fa436bfac03c7c3784a9c 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -1897,7 +1897,7 @@ OP_E607E0 (void)
   temp = load_mem (State.regs[ OP[0] ], 1);
   
   PSW &= ~PSW_Z;
-  if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
+  if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
     PSW |= PSW_Z;
   
   trace_output (OP_BIT);
@@ -1924,7 +1924,7 @@ OP_22207E0 (void)
                                                \
   trace_input (name, OP_BIT_CHANGE, 0);                \
                                                \
-  bit  = 1 << State.regs[ OP[1] & 0x7 ];       \
+  bit  = 1 << (State.regs[ OP[1] ] & 0x7);     \
   temp = load_mem (State.regs[ OP[0] ], 1);    \
                                                \
   PSW &= ~PSW_Z;                               \