Merge ktlim@zamp:./local/clean/tmp/test-regress

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5

diff --combined src/cpu/o3/alpha/cpu_impl.hh
index 15b50cb15c7a92116c2d97e8c8208d07a6db73a4,f5c39482678c4cb822ab03b1b7a09e549b9a58c6..b2ef78360a2c0c7b28a46bd65cdcfeafe71357d0
--- 1/src/cpu/o3/alpha/cpu_impl.hh
--- 2/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@@ -231,7 -231,7 +231,7 @@@ Faul
  AlphaO3CPU<Impl>::hwrei(unsigned tid)
  {
      // Need to clear the lock flag upon returning from an interrupt.
 -    this->lockFlag = false;
 +    this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
  
      this->thread[tid]->kernelStats->hwrei();
  
@@@ -266,9 -266,17 +266,17 @@@ AlphaO3CPU<Impl>::simPalCheck(int palFu
      return true;
  }
  
+ template <class Impl>
+ Fault
+ AlphaO3CPU<Impl>::getInterrupts()
+ {
+     // Check if there are any outstanding interrupts
+     return this->interrupts.getInterrupt(this->threadContexts[0]);
+ }
+ 
  template <class Impl>
  void
- AlphaO3CPU<Impl>::processInterrupts()
+ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
  {
      // Check for interrupts here.  For now can copy the code that
      // exists within isa_fullsys_traits.hh.  Also assume that thread 0
@@@ -276,14 -284,12 +284,12 @@@
      // @todo: Possibly consolidate the interrupt checking code.
      // @todo: Allow other threads to handle interrupts.
  
-     // Check if there are any outstanding interrupts
-     //Handle the interrupts
-     Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
+     assert(interrupt != NoFault);
+     this->interrupts.updateIntrInfo(this->threadContexts[0]);
  
-     if (interrupt != NoFault) {
-         this->checkInterrupts = false;
-         this->trap(interrupt, 0);
-     }
+     DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
+     this->checkInterrupts = false;
+     this->trap(interrupt, 0);
  }
  
  #endif // FULL_SYSTEM

diff --combined src/cpu/o3/fetch_impl.hh
index 350ecd52dae83ef7db5cc56892eaa587e827ded5,b1fae8cf058137baff742c41aab303db88c94d9f..a5478d4f89a118921fbaf40e32613fb3bb881c09
--- 1/src/cpu/o3/fetch_impl.hh
--- 2/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@@ -62,8 -62,7 +62,8 @@@ template<class Impl
  void
  DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
  {
 -    warn("Default fetch doesn't update it's state from a functional call.");
 +    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
 +            "functional call.");
  }
  
  template<class Impl>
@@@ -80,7 -79,6 +80,7 @@@ template<class Impl
  bool
  DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
  {
 +    DPRINTF(Fetch, "Received timing\n");
      if (pkt->isResponse()) {
          fetch->processCacheCompletion(pkt);
      }
@@@ -561,27 -559,36 +561,36 @@@ DefaultFetch<Impl>::fetchCacheLine(Add
      Fault fault = NoFault;
  
      //AlphaDep
-     if (cacheBlocked || isSwitchedOut() ||
-             (interruptPending && (fetch_PC & 0x3))) {
+     if (cacheBlocked) {
+         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
+                 tid);
+         return false;
+     } else if (isSwitchedOut()) {
+         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
+                 tid);
+         return false;
+     } else if (interruptPending && !(fetch_PC & 0x3)) {
          // Hold off fetch from getting new instructions when:
          // Cache is blocked, or
          // while an interrupt is pending and we're not in PAL mode, or
          // fetch is switched out.
+         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
+                 tid);
          return false;
      }
  
      // Align the fetch PC so it's at the start of a cache block.
-     fetch_PC = icacheBlockAlignPC(fetch_PC);
+     Addr block_PC = icacheBlockAlignPC(fetch_PC);
  
      // If we've already got the block, no need to try to fetch it again.
-     if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
+     if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
          return true;
      }
  
      // Setup the memReq to do a read of the first instruction's address.
      // Set the appropriate read size and flags as well.
      // Build request here.
-     RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
+     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
                                       fetch_PC, cpu->readCpuId(), tid);
  
      memReq[tid] = mem_req;
@@@ -611,7 -618,7 +620,7 @@@
                                          Packet::ReadReq, Packet::Broadcast);
          data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
  
-         cacheDataPC[tid] = fetch_PC;
+         cacheDataPC[tid] = block_PC;
          cacheDataValid[tid] = false;
  
          DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
@@@ -1052,12 -1059,16 +1061,16 @@@ DefaultFetch<Impl>::fetch(bool &status_
      } else {
          if (fetchStatus[tid] == Idle) {
              ++fetchIdleCycles;
+             DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
          } else if (fetchStatus[tid] == Blocked) {
              ++fetchBlockedCycles;
+             DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
          } else if (fetchStatus[tid] == Squashing) {
              ++fetchSquashCycles;
+             DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
          } else if (fetchStatus[tid] == IcacheWaitResponse) {
              ++icacheStallCycles;
+             DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
          }
  
          // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
@@@ -1160,8 -1171,8 +1173,8 @@@
              fetch_PC = next_PC;
  
              if (instruction->isQuiesce()) {
 -//                warn("%lli: Quiesce instruction encountered, halting fetch!",
 -//                     curTick);
 +                DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
 +                        curTick);
                  fetchStatus[tid] = QuiescePending;
                  ++numInst;
                  status_change = true;
@@@ -1275,13 -1286,11 +1288,13 @@@
  
          fetchStatus[tid] = TrapPending;
          status_change = true;
 -
 -//        warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
  #else // !FULL_SYSTEM
 -        warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
 +        fetchStatus[tid] = TrapPending;
 +        status_change = true;
 +
  #endif // FULL_SYSTEM
 +        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
 +                tid, fault->name(), PC[tid]);
      }
  }
  

diff --combined src/cpu/simple/atomic.cc
index e9679cc7c53ede7d3a7f0fbdbbbba4449d5449b3,f94ea091748720278f70b1c7af052c9ef3b85e6e..58dc1fe5f6b09accd89efb43294182a03aa55a65
--- 1/src/cpu/simple/atomic.cc
--- 2/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@@ -213,6 -213,9 +213,9 @@@ AtomicSimpleCPU::takeOverFrom(BaseCPU *
              break;
          }
      }
+     if (_status != Running) {
+         _status = Idle;
+     }
  }
  
  
@@@ -500,10 -503,6 +503,10 @@@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicS
      SimObjectParam<TheISA::ITB *> itb;
      SimObjectParam<TheISA::DTB *> dtb;
      Param<Tick> profile;
 +
 +    Param<bool> do_quiesce;
 +    Param<bool> do_checkpoint_insts;
 +    Param<bool> do_statistics_insts;
  #else
      SimObjectParam<Process *> workload;
  #endif // FULL_SYSTEM
@@@ -536,9 -535,6 +539,9 @@@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimp
      INIT_PARAM(itb, "Instruction TLB"),
      INIT_PARAM(dtb, "Data TLB"),
      INIT_PARAM(profile, ""),
 +    INIT_PARAM(do_quiesce, ""),
 +    INIT_PARAM(do_checkpoint_insts, ""),
 +    INIT_PARAM(do_statistics_insts, ""),
  #else
      INIT_PARAM(workload, "processes to run"),
  #endif // FULL_SYSTEM
@@@ -576,9 -572,6 +579,9 @@@ CREATE_SIM_OBJECT(AtomicSimpleCPU
      params->itb = itb;
      params->dtb = dtb;
      params->profile = profile;
 +    params->do_quiesce = do_quiesce;
 +    params->do_checkpoint_insts = do_checkpoint_insts;
 +    params->do_statistics_insts = do_statistics_insts;
  #else
      params->process = workload;
  #endif