(no commit message)

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 5bbbfd62a99cfa5fe4fa1065b465cce49f542fa8..b33e80a334d783edb92f08e79a7fd627b61a5ee2 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -216,8 +216,7 @@ another mode selection would be CRs not Ints.
 
 # int min/max
 
-required for
-the [[sv/av_opcodes]]
+required for the [[sv/av_opcodes]]
 
 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
 
@@ -238,6 +237,16 @@ uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
 }
 ```
 
+# int average
+
+required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
+but not scalar
+
+```
+uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
+     return (rs1 + rs2 + 1) >> 1:
+}
+```
 
 ## cmix