ac/gpu_info: add has_bo_metadata

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6f2fea895be3179b417e06ba6dad545a94f3fc3f..68750b2db283379270c546d91c192ea6d54d5fcd 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -319,6 +319,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->kernel_flushes_hdp_before_ib = true;
        info->htile_cmask_support_1d_tiling = true;
        info->si_TA_CS_BC_BASE_ADDR_allowed = true;
+       info->has_bo_metadata = true;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -469,6 +470,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
        printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
        printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
+       printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index bc6350b5625110d21c4824d87fb88719141e4a7c..340c368bda3cfe1c69dcca44380e081fae3cdb9e 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -99,6 +99,7 @@ struct radeon_info {
        bool                        kernel_flushes_hdp_before_ib;
        bool                        htile_cmask_support_1d_tiling;
        bool                        si_TA_CS_BC_BASE_ADDR_allowed;
+       bool                        has_bo_metadata;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 144516e3a5ea77560c1ba362100baf05fa026c75..d2814c4f300529f1df86f244e2867315f893f865 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -608,8 +608,7 @@ static void si_query_opaque_metadata(struct si_screen *sscreen,
        uint32_t desc[8], i;
        bool is_array = util_texture_is_array(res->target);
 
-       /* DRM 2.x.x doesn't support this. */
-       if (sscreen->info.drm_major != 3)
+       if (!sscreen->info.has_bo_metadata)
                return;
 
        assert(rtex->dcc_separate_buffer == NULL);

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 6040134c2da0b27f5f2fc9c090939b634ecc9c14..d7ecfe9f2400a11222cc8e32a59068930655ce34 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -533,6 +533,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
+    ws->info.has_bo_metadata = false;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;