Clarify a few comments. NFC.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 2075b90c997d152f144b92aa1194930963d4a730..fb600034c8f5645552ba99b6ddcdb5422619068b 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -576,7 +576,7 @@ class _RHSValueCompiler(_ValueCompiler):
         res_bits, res_sign = value.shape()
         res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
         # Note: Verilog's x[o+:w] construct produces a $shiftx cell, not a $shift cell.
-        # However, Migen's semantics defines the out-of-range bits to be zero, so it is correct
+        # However, nMigen's semantics defines the out-of-range bits to be zero, so it is correct
         # to use a $shift cell here instead, even though it produces less idiomatic Verilog.
         self.s.rtlil.cell("$shift", ports={
             "\\A": self(lhs),

diff --git a/nmigen/build/run.py b/nmigen/build/run.py
index 93aa4df06dee4e9b04e07867973618078ef28115..82c27ad2239be583ef4dd8e5d74032f79e09cf73 100644 (file)
--- a/nmigen/build/run.py
+++ b/nmigen/build/run.py
@@ -88,11 +88,8 @@ class BuildPlan:
             if run_script:
                 if sys.platform.startswith("win32"):
                     # Without "call", "cmd /c {}.bat" will return 0.
-                    # See https://stackoverflow.com/a/30736987 for a detailed
-                    # explanation of why, including disassembly/decompilation
-                    # of relevant code in cmd.exe.
-                    # Running the script manually from a command prompt is
-                    # unaffected- i.e. "call" is not required.
+                    # See https://stackoverflow.com/a/30736987 for a detailed explanation of why.
+                    # Running the script manually from a command prompt is unaffected.
                     subprocess.check_call(["cmd", "/c", "call {}.bat".format(self.script)])
                 else:
                     subprocess.check_call(["sh", "{}.sh".format(self.script)])