(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index ae0459ed489ecc90534b119c5f08dff0adf89ac9..e0b3bc63c891bf359123adf29b5669d6b13d1cc1 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -173,7 +173,8 @@ conceptualise what the effect of Twin Predication is, but it actually
 goes much further: in *any* twin-predicated instruction (extsw, fmv)
 it is possible to apply one predicate to the source register (compressing
 the source element array) and another *completely separate* predicate
-to the destination register, *in one instruction* and not just on Load/Stores.
+to the destination register, not just on Load/Stores but on *arithmetic*
+operations.
 
 No other Vector ISA in the world has this capability.  All true Vector
 ISAs have Predicate Masks: it is an absolutely essential characteristic.
@@ -189,6 +190,10 @@ is that there just wasn't enough space in the 24-bits of the SVP64 Prefix.
 Consequently, when using a given instruction, it is necessary to look
 up in the ISA Tables whether it is 1P or 2P. caveat emptor!
 
+Also worth a special mention: all Load/Store operations are Twin-Predicated.
+In other words: one Predicate applies to the Array of Memory Addresses,
+whilst the other Predicate applies to the Array of Memory Data.
+
 # CR weird instructions
 
 [[sv/int_cr_predication]] is by far the biggest violator of the SVP64