--- /dev/null
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+import m5
+from m5.objects import *
+
+import argparse
+
+parser = argparse.ArgumentParser(description='Simple memory tester')
+parser.add_argument('--bandwidth', default=None)
+parser.add_argument('--latency', default=None)
+parser.add_argument('--latency_var', default=None)
+
+args = parser.parse_args()
+
+# both traffic generator and communication monitor are only available
+# if we have protobuf support, so potentially skip this test
+# require_sim_object("TrafficGen")
+# require_sim_object("CommMonitor")
+# This needs to be fixed in the new infrastructure
+
+# even if this is only a traffic generator, call it cpu to make sure
+# the scripts are happy
+cpu = TrafficGen(
+ config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
+ "tgen-simple-mem.cfg"))
+
+class MyMem(SimpleMemory):
+ if args.bandwidth:
+ bandwidth = args.bandwidth
+ if args.latency:
+ latency = args.latency
+ if args.latency_var:
+ latency_var = args.latency_var
+
+# system simulated
+system = System(cpu = cpu, physmem = MyMem(),
+ membus = IOXBar(width = 16),
+ clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ VoltageDomain()))
+
+# add a communication monitor, and also trace all the packets and
+# calculate and verify stack distance
+system.monitor = CommMonitor()
+system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
+system.monitor.stackdist = StackDistProbe(verify = True)
+
+# connect the traffic generator to the bus via a communication monitor
+system.cpu.port = system.monitor.slave
+system.monitor.master = system.membus.slave
+
+# connect the system port even if it is not used in this example
+system.system_port = system.membus.slave
+
+# connect memory to the membus
+system.physmem.port = system.membus.master
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+
+m5.instantiate()
+exit_event = m5.simulate(100000000000)
+
+print(exit_event.getCause())
--- /dev/null
+# Copyright (c) 2018 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+'''
+Test file for simple memory test
+TODO: Add stats checking
+'''
+from testlib import *
+
+gem5_verify_config(
+ name='simple_mem_default',
+ verifiers=(), # No need for verfiers this will return non-zero on fail
+ config=joinpath(getcwd(), 'simple-run.py'),
+ config_args = [],
+ valid_isas=(constants.null_tag,),
+)
+
+simple_mem_params = [
+ ('inf-bandwidth', {'bandwidth': '0GB/s'}),
+ ('low-latency', {'latency': '1ns'}),
+ ('high-latency', {'latency': '1us'}),
+ ('low-bandwidth', {'bandwidth': '1MB/s'}),
+ ('high-var', {'latency_var': '100ns'})
+ ]
+
+
+for name, params in simple_mem_params:
+ args = ['--' + key + '=' + val for key,val in params.iteritems()]
+
+ gem5_verify_config(
+ name='simple_mem_' + name,
+ verifiers=(), # No need for verfiers this will return non-zero on fail
+ config=joinpath(getcwd(), 'simple-run.py'),
+ config_args = args,
+ valid_isas=(constants.null_tag,),
+ )
+
--- /dev/null
+# This format supports comments using the '#' symbol as the leading
+# character of the line
+#
+# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
+# where the states are the nodes in the graph, init describes what
+# state to start in, and transition describes the edges of the graph.
+#
+# STATE <id> <duration (ticks)> <type>
+#
+# State IDLE idles
+#
+# States LINEAR and RANDOM have additional <percent reads> <start addr>
+# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
+# <data limit (bytes)>
+#
+# State TRACE plays back a pre-recorded trace once
+#
+# Addresses are expressed as decimal numbers. The period in the linear
+# and random state is from a uniform random distribution over the
+# interval. If a specific value is desired, then the min and max can
+# be set to the same value.
+STATE 0 1000000 TRACE tgen-simple-mem.trc 100
+STATE 1 100000000 RANDOM 0 0 134217728 64 30000 30000 0
+STATE 2 1000000000 IDLE
+STATE 3 100000000 LINEAR 0 0 134217728 64 30000 30000 0
+STATE 4 1000000 IDLE
+INIT 0
+TRANSITION 0 1 1
+TRANSITION 1 2 1
+TRANSITION 2 3 0.5
+TRANSITION 2 4 0.5
+TRANSITION 3 2 1
+TRANSITION 4 4 1
projects / gem5.git / commitdiff