+2013-05-05 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (*vec_extract<ssevecmodelower>_0): Merge
+ from sse2_stored and *sse2_storeq_rex64 using SWI48 mode iterator.
+ Add m->r,x alternatives.
+ (*vec_extract<ssevecmodelower>_0 splitters): Merge V2DI and V4SI
+ splitters using SWI48x mode iterator.
+ (*vec_extract_v2di_0_sse): Rename from *sse2_storeq. Disable for
+ TARGET_64BIT. Add m->x alternative.
+ (*vec_extractv4si_mem): Rename from *vec_ext_v4si_mem.
+ Add o->x alternative. Enable for TARGET_SSE.
+ (sse_storeq): Remove expander.
+ (*vec_extractv2di_1): Enable for TARGET_SSE. Split alternatives
+ with memory input operand.
+ (*vec_extractv2di_1 splitter): New.
+ (*vec_extractv4sf_mem): Rename from *vec_extract_v4sf_mem.
+ * config/i386/i386.md (ssevecmodelower): New mode attribute.
+
2013-05-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.c (INT_P): Reformat. Delete obsolete comment.
logical_const_operand): Delete "CONST_DOUBLE" case.
* config/rs6000/rs6000.c (num_insns_constant_wide): Delete
"HOST_BITS_PER_WIDE_INT == 64" test.
- (num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode
- case.
+ (num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode case.
(build_mask64_2_operands): Delete "HOST_BITS_PER_WIDE_INT >= 64" test.
(rs6000_emit_set_const): Delete CONST_DOUBLE case.
(rs6000_emit_set_long_const): Delete "HOST_BITS_PER_WIDE_INT >= 64"
2013-05-03 Guozhi Wei <carrot@google.com>
* coverage.c (coverage_obj_init): Move the construction of gcov
- constructor to
- (build_init_ctor): here.
+ constructor to ...
+ (build_init_ctor): ... here.
2013-05-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
2013-05-03 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/57130
- * combine.c (make_compound_operation) <case SUBREG>: Pass
- SET instead of COMPARE as in_code to the recursive call
- if needed.
+ * combine.c (make_compound_operation) <case SUBREG>: Pass SET instead
+ of COMPARE as in_code to the recursive call if needed.
2013-05-03 Uros Bizjak <ubizjak@gmail.com>
(set_attr "prefix" "maybe_vex,*,*")
(set_attr "mode" "V4SF,*,*")])
-(define_insn_and_split "*vec_extract_v4sf_mem"
+(define_insn_and_split "*vec_extractv4sf_mem"
[(set (match_operand:SF 0 "register_operand" "=x,*r,f")
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand" "o,o,o")
- (parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
+ (vec_select:SF
+ (match_operand:V4SF 1 "memory_operand" "o,o,o")
+ (parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
"TARGET_SSE"
"#"
"&& reload_completed"
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-;; It must come before *vec_extractv2di_1_rex64 since it is preferred.
+;; It must come before *vec_extractv2di_1 since it is preferred.
(define_insn "*sse4_1_pextrq"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(vec_select:DI
(set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex")
(set_attr "mode" "TI,TI,V4SF,SF,SF")])
-(define_insn_and_split "sse2_stored"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=xm,r")
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x,Yj")
- (parallel [(const_int 0)])))]
- "TARGET_SSE"
- "#"
- "&& reload_completed
- && (TARGET_INTER_UNIT_MOVES_FROM_VEC
- || MEM_P (operands [0])
- || !GENERAL_REGNO_P (true_regnum (operands [0])))"
- [(set (match_dup 0) (match_dup 1))]
- "operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));")
-
-(define_insn_and_split "*vec_ext_v4si_mem"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "o")
- (parallel [(match_operand 2 "const_0_to_3_operand")])))]
- ""
- "#"
- "reload_completed"
- [(const_int 0)]
-{
- int i = INTVAL (operands[2]);
-
- emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
- DONE;
-})
-
-(define_expand "sse_storeq"
- [(set (match_operand:DI 0 "nonimmediate_operand")
- (vec_select:DI
- (match_operand:V2DI 1 "register_operand")
+(define_insn "*vec_extract<ssevecmodelower>_0"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=x,m,r ,r")
+ (vec_select:SWI48
+ (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm,x,Yj,m")
(parallel [(const_int 0)])))]
- "TARGET_SSE")
+ "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "#")
-(define_insn "*sse2_storeq_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=xm,*r,r")
+(define_insn "*vec_extractv2di_0_sse"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x,Yj,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0)])))]
- "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- #
- #
- mov{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "*,*,imov")
- (set_attr "mode" "*,*,DI")])
+ "TARGET_SSE && !TARGET_64BIT
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "#")
-(define_insn "*sse2_storeq"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=xm")
- (vec_select:DI
- (match_operand:V2DI 1 "register_operand" "x")
+(define_split
+ [(set (match_operand:SWI48x 0 "register_operand")
+ (vec_select:SWI48x
+ (match_operand:<ssevecmode> 1 "memory_operand")
(parallel [(const_int 0)])))]
- "TARGET_SSE"
- "#")
+ "TARGET_SSE && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[1] = adjust_address (operands[1], <MODE>mode, 0);")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand")
- (vec_select:DI
- (match_operand:V2DI 1 "register_operand")
+ [(set (match_operand:SWI48x 0 "nonimmediate_operand")
+ (vec_select:SWI48x
+ (match_operand:<ssevecmode> 1 "register_operand")
(parallel [(const_int 0)])))]
- "TARGET_SSE
- && reload_completed
+ "TARGET_SSE && reload_completed
&& (TARGET_INTER_UNIT_MOVES_FROM_VEC
- || MEM_P (operands [0])
- || !GENERAL_REGNO_P (true_regnum (operands [0])))"
+ || !GENERAL_REG_P (operands [0]))"
[(set (match_dup 0) (match_dup 1))]
- "operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
+ "operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));")
+
+(define_insn_and_split "*vec_extractv4si_mem"
+ [(set (match_operand:SI 0 "register_operand" "=x,r")
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "o,o")
+ (parallel [(match_operand 2 "const_0_to_3_operand")])))]
+ "TARGET_SSE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
+})
(define_insn "*vec_extractv2di_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,x,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,r")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,x,o,o")
(parallel [(const_int 1)])))]
- "(TARGET_64BIT || TARGET_SSE)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
%vmovhps\t{%1, %0|%0, %1}
psrldq\t{$8, %0|%0, 8}
vpsrldq\t{$8, %1, %0|%0, %1, 8}
- %vmovq\t{%H1, %0|%0, %H1}
movhlps\t{%1, %0|%0, %1}
- movlps\t{%H1, %0|%0, %H1}
- mov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx,x64")
- (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov,imov")
- (set_attr "length_immediate" "*,1,1,*,*,*,*")
- (set_attr "memory" "*,none,none,*,*,*,*")
- (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig,orig")
- (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF,DI")])
+ #
+ #"
+ [(set_attr "isa" "*,sse2_noavx,avx,noavx,*,x64")
+ (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,imov")
+ (set_attr "length_immediate" "*,1,1,*,*,*")
+ (set_attr "memory" "*,none,none,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,vex,orig,*,*")
+ (set_attr "mode" "V2SF,TI,TI,V4SF,DI,DI")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (vec_select:DI
+ (match_operand:V2DI 1 "memory_operand")
+ (parallel [(const_int 1)])))]
+ "TARGET_SSE && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ "operands[1] = adjust_address (operands[1], DImode, 8);")
(define_insn "*vec_dupv4si"
[(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
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