r600: add new relocs for tiling support

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>

diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 172f85eb264a87100e7dcb27f4db8ad5b869694b..619678214f0603edd6bd0d13f6acdaf112ed4466 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -390,13 +390,20 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
                         0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     END_BATCH();
 
-    BEGIN_BATCH_NO_AUTOSTATE(12);
+    BEGIN_BATCH_NO_AUTOSTATE(9);
     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
-    R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
     END_BATCH();
 
+    BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+    R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
+    R600_OUT_BATCH_RELOC(0,
+                        bo,
+                        0,
+                        0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+    END_BATCH();
+
     COMMIT_BATCH();
 
 }
@@ -1447,7 +1454,7 @@ set_default_state(context_t *context)
            SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
     }
 
-    BEGIN_BATCH_NO_AUTOSTATE(117);
+    BEGIN_BATCH_NO_AUTOSTATE(114);
     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
     R600_OUT_BATCH(sq_config);
     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
@@ -1477,7 +1484,6 @@ set_default_state(context_t *context)
                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
     R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
     R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
-    R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
     R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
     R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
     R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
@@ -1607,7 +1613,7 @@ unsigned r600_blit(GLcontext *ctx,
     /* Flush is needed to make sure that source buffer has correct data */
     radeonFlush(ctx);
 
-    rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__);
+    rcommonEnsureCmdBufSpace(&context->radeon, 305, __FUNCTION__);
 
     /* load shaders */
     load_shaders(context->radeon.glCtx);
@@ -1616,7 +1622,7 @@ unsigned r600_blit(GLcontext *ctx,
         return GL_FALSE;
 
     /* set clear state */
-    /* 117 */
+    /* 114 */
     set_default_state(context);
 
     /* shaders */
@@ -1632,7 +1638,7 @@ unsigned r600_blit(GLcontext *ctx,
     set_tex_sampler(context);
 
     /* dst */
-    /* 27 */
+    /* 31 */
     set_render_target(context, dst_bo, dst_mesaformat,
                      dst_pitch, dst_width, dst_height, dst_offset);
     /* scissors */

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index cefda3ac4bae9431b214e797f8142d08feaa9e89..1e955b93b2b372a63c807835eb3872d3b81dc655 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -617,18 +617,25 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
 
        r700SetDepthTarget(context);
 
-        BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
+        BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
        R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
        R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
        R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
-       R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
+       R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
        R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
-       R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
        R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
                             rrb->bo,
                             r700->DB_DEPTH_BASE.u32All,
                             0, RADEON_GEM_DOMAIN_VRAM, 0);
         END_BATCH();
+        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+       R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
+       R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
+       R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
+                            rrb->bo,
+                            r700->DB_DEPTH_INFO.u32All,
+                            0, RADEON_GEM_DOMAIN_VRAM, 0);
+        END_BATCH();
 
        if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
            (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
@@ -687,27 +694,35 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
        R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
        R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
-       R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
+       R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
                             rrb->bo,
-                            r700->render_target[id].CB_COLOR0_BASE.u32All,
+                            r700->render_target[id].CB_COLOR0_TILE.u32All,
                             0, RADEON_GEM_DOMAIN_VRAM, 0);
        END_BATCH();
        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
        R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
        R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
-       R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
+       R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
                             rrb->bo,
-                            r700->render_target[id].CB_COLOR0_BASE.u32All,
+                            r700->render_target[id].CB_COLOR0_FRAG.u32All,
                             0, RADEON_GEM_DOMAIN_VRAM, 0);
         END_BATCH();
 
-        BEGIN_BATCH_NO_AUTOSTATE(12);
+        BEGIN_BATCH_NO_AUTOSTATE(9);
        R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
        R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
-       R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
        R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
         END_BATCH();
 
+       BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+       R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
+       R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
+                            rrb->bo,
+                            r700->render_target[id].CB_COLOR0_INFO.u32All,
+                            0, RADEON_GEM_DOMAIN_VRAM, 0);
+
+        END_BATCH();
+
        COMMIT_BATCH();
 
 }
@@ -1567,7 +1582,7 @@ void r600InitAtoms(context_t *context)
        ALLOC_STATE(sq, always, 34, r700SendSQConfig);
        ALLOC_STATE(db, always, 17, r700SendDBState);
        ALLOC_STATE(stencil, always, 4, r700SendStencilState);
-       ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
+       ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
        ALLOC_STATE(sc, always, 15, r700SendSCState);
        ALLOC_STATE(scissor, always, 22, r700SendScissorState);
        ALLOC_STATE(aa, always, 12, r700SendAAState);
@@ -1578,7 +1593,7 @@ void r600InitAtoms(context_t *context)
        ALLOC_STATE(poly, always, 10, r700SendPolyState);
        ALLOC_STATE(cb, cb, 18, r700SendCBState);
        ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
-       ALLOC_STATE(cb_target, always, 29, r700SendRenderTargetState);
+       ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
        ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
        ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
        ALLOC_STATE(sx, always, 9, r700SendSXState);