boards/targets: keep attributes are no longer needed since automatically added when...

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index fec7903093a558f12852d1958dae94461ca5dd9f..63a6ea449c65617b7ec4a1f68feb7362b0c56cc7 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -32,10 +32,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-        self.cd_sys4x_dqs.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
@@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 010331cf344d2ddb76171ac80ec334e56c209e83..f05fdf43f88b448ea451e2315512886e4d6e826b 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -25,10 +25,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys_ps.clk.attr.add("keep")
-        self.cd_por.clk.attr.add("keep")
-
         # Power on reset
         rst_n = Signal()
         self.sync.por += rst_n.eq(1)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index ff1a24a2b2b2a42d74393efa0d5eb71cef99a00a..0a7e95a4f8c4a1ad2fff5f2405571345c41cd451 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -29,9 +29,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
         pll.register_clkin(platform.request("clk200"), 200e6)
@@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 07d6856ff11333a6c7469cad886fdfcad9fddc9c..8716072108ccadebbb5e4ee1233c9d090b852b34 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -31,9 +31,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk200"), 200e6)
@@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index d7d2fbda08568147e668facb77bbc05044e5ac21..1243454fab249862efa991f00f6764f2b3f69e07 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -30,9 +30,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
@@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 8c7230ec1502819094e8749973542c5e883c0f48..04f71c592f062a7f5713dd153e72e7640b17c619 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -29,9 +29,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys_ps.clk.attr.add("keep")
-
         self.submodules.pll = pll = S6PLL(speedgrade=-1)
         pll.register_clkin(platform.request("clk32"), 32e6)
         pll.create_clkout(self.cd_sys,    clk_freq)

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index bf54283031a2600868f8610f226266f160e56f78..7fecb76ab482566ddeaeb69996747960034c4dc7 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -32,10 +32,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-        self.cd_sys4x_dqs.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         pll.register_clkin(platform.request("clk50"), 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
@@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index be2e689314e37ab237d606451f79024f42e19312..e19c6f3a4550c94e0ccd51a03fcce0453361bf94 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -31,10 +31,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys2x.clk.attr.add("keep")
-        self.cd_sys2x_dqs.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
@@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 666a4724fc344929d43482f4287b43a5c4ef68dc..fa423ac6288ffbee67718aca469ff2ffca25fd6d 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -31,10 +31,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys4x.clk.attr.add("keep")
-        self.cd_sys4x_dqs.clk.attr.add("keep")
-
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
@@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index f14a7aae59bdc4207e35c08ce1e36fe2a6b94852..94994a77f28162dbccde774870278f8180d0e167 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -27,9 +27,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys_ps.clk.attr.add("keep")
-
         # clk / rst
         clk25 = platform.request("clk25")
         rst   = platform.request("rst")

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 3843b4544364f960439620c25575321ca124c891..81ad572b0b0135d771e4eb373b03b8898212dd80 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -35,12 +35,6 @@ class _CRG(Module):
 
         # # #
 
-        self.cd_init.clk.attr.add("keep")
-        self.cd_por.clk.attr.add("keep")
-        self.cd_sys.clk.attr.add("keep")
-        self.cd_sys2x.clk.attr.add("keep")
-        self.cd_sys2x_i.clk.attr.add("keep")
-
         self.stop = Signal()
 
         # clk / rst
@@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 
-        self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)