ralloc_steal(mem_ctx, nir);
prog_data.inputs_read = nir->info.inputs_read;
- if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
- pipeline->writes_point_size = true;
brw_compute_vue_map(&pipeline->device->info,
&prog_data.base.vue_map,
if (module->nir == NULL)
ralloc_steal(mem_ctx, nir);
- if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
- pipeline->writes_point_size = true;
-
brw_compute_vue_map(&pipeline->device->info,
&prog_data.base.vue_map,
nir->info.outputs_written,
anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
pipeline->use_repclear = extra && extra->use_repclear;
- pipeline->writes_point_size = false;
/* When we free the pipeline, we detect stages based on the NULL status
* of various prog_data pointers. Make them NULL by default.
/* uint32_t AALineDistanceMode; */
/* uint32_t VertexSubPixelPrecisionSelect; */
- .UsePointWidthState = !pipeline->writes_point_size,
+ .UsePointWidthState = false,
.PointWidth = 1.0,
.GlobalDepthOffsetEnableSolid = info->depthBiasEnable,
.GlobalDepthOffsetEnableWireframe = info->depthBiasEnable,
.TriangleStripListProvokingVertexSelect = 0,
.LineStripListProvokingVertexSelect = 0,
.TriangleFanProvokingVertexSelect = 1,
- .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
+ .PointWidthSource = Vertex,
.PointWidth = 1.0,
};