return file == GRF || file == UNIFORM;
}
+bool
+fs_reg::is_accumulator() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+}
+
int
fs_visitor::type_size(const struct glsl_type *type)
{
bool is_null() const;
bool is_valid_3src() const;
bool is_contiguous() const;
+ bool is_accumulator() const;
fs_reg &apply_stride(unsigned stride);
/** Smear a channel of the reg to all channels. */
swizzles[2], swizzles[3]);
}
+bool
+src_reg::is_accumulator() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+}
+
+
void
dst_reg::init()
{
fixed_hw_reg.nr == BRW_ARF_NULL;
}
+bool
+dst_reg::is_accumulator() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+}
+
bool
vec4_instruction::is_send_from_grf()
{
bool equals(src_reg *r);
bool is_zero() const;
bool is_one() const;
+ bool is_accumulator() const;
src_reg(class vec4_visitor *v, const struct glsl_type *type);
explicit dst_reg(src_reg reg);
bool is_null() const;
+ bool is_accumulator() const;
int writemask; /**< Bitfield of WRITEMASK_[XYZW] */