+2003-09-30 Chris Demetriou <cgd@broadcom.com>
+
+ * config/tc-mips.c (mips_ip): Capitalize first word of
+ existing condition code warning, and add condition code
+ warnings for .ps instructions, and for bc1any[24][tf].
+
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* NEWS: Mention support for MIPS64 Release 2.
}
while (ISDIGIT (*s));
if (regno > 7)
- as_bad (_("invalid condition code register $fcc%d"), regno);
+ as_bad (_("Invalid condition code register $fcc%d"), regno);
+ if ((strcmp(str + strlen(str) - 3, ".ps") == 0
+ || strcmp(str + strlen(str) - 5, "any2f") == 0
+ || strcmp(str + strlen(str) - 5, "any2t") == 0)
+ && (regno & 1) != 0)
+ as_warn(_("Condition code register should be even for %s, was %d"),
+ str, regno);
+ if ((strcmp(str + strlen(str) - 5, "any4f") == 0
+ || strcmp(str + strlen(str) - 5, "any4t") == 0)
+ && (regno & 3) != 0)
+ as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
+ str, regno);
if (*args == 'N')
ip->insn_opcode |= regno << OP_SH_BCC;
else
+2003-09-30 Chris Demetriou <cgd@broadcom.com>
+
+ * lib/gas-defs.exp (run_dump_test): If stderr file is specified
+ and there was no stderr output, compare anyway (i.e., cause a
+ test failure).
+ * gas/mips/mips64-mips3d.s: Add some new instructions to test warnings.
+ * gas/mips/mips64-mips3d.l: New file.
+ * gas/mips/mips64-mips3d.d: Use mips64-mips3d.l, and update for
+ changes to mips64-mips3d.s.
+ * gas/mips/mips64-mips3d-incl.d: Likewise.
+ * gas/mips/set-arch.l: New file.
+ * gas/mips/set-arch.d: Specify set-arch.l as stderr output to check.
+ * gas/mips/mips5.l: Make error messages match source.
+
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
.*: Assembler messages:
-.*:61: Warning: Condition flag should be even for c.eq.ps, was 3
-.*:62: Warning: Condition flag should be even for movf.ps, was 3
+.*:61: Warning: Condition code register should be even for c.eq.ps, was 3
+.*:62: Warning: Condition code register should be even for movf.ps, was 3
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS MIPS64 MIPS-3D ASE instructions
#source: mips64-mips3d.s
+#stderr: mips64-mips3d.l
# Check MIPS64 MIPS-3D ASE instruction assembly and disassembly
# Same as mips64-mips3d.d, but does not need -mips3d assembler
0+01f4 <[^>]*> 4633411f rsqrt2\.d \$f4,\$f8,\$f19
0+01f8 <[^>]*> 4613411f rsqrt2\.s \$f4,\$f8,\$f19
0+01fc <[^>]*> 46d3411f rsqrt2\.ps \$f4,\$f8,\$f19
+0+0200 <[^>]*> 4524ff7f bc1any2f \$fcc1,0+0000 <text_label>
+0+0204 <[^>]*> 00000000 nop
+0+0208 <[^>]*> 452dff7d bc1any2t \$fcc3,0+0000 <text_label>
+0+020c <[^>]*> 00000000 nop
+0+0210 <[^>]*> 4544ff7b bc1any4f \$fcc1,0+0000 <text_label>
+0+0214 <[^>]*> 00000000 nop
+0+0218 <[^>]*> 4549ff79 bc1any4t \$fcc2,0+0000 <text_label>
+0+021c <[^>]*> 00000000 nop
\.\.\.
#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64
#name: MIPS MIPS64 MIPS-3D ASE instructions (-mips3d flag)
#as: -mips64 -mips3d
+#stderr: mips64-mips3d.l
# Check MIPS64 MIPS-3D ASE instruction assembly and disassembly
0+01f4 <[^>]*> 4633411f rsqrt2\.d \$f4,\$f8,\$f19
0+01f8 <[^>]*> 4613411f rsqrt2\.s \$f4,\$f8,\$f19
0+01fc <[^>]*> 46d3411f rsqrt2\.ps \$f4,\$f8,\$f19
+0+0200 <[^>]*> 4524ff7f bc1any2f \$fcc1,0+0000 <text_label>
+0+0204 <[^>]*> 00000000 nop
+0+0208 <[^>]*> 452dff7d bc1any2t \$fcc3,0+0000 <text_label>
+0+020c <[^>]*> 00000000 nop
+0+0210 <[^>]*> 4544ff7b bc1any4f \$fcc1,0+0000 <text_label>
+0+0214 <[^>]*> 00000000 nop
+0+0218 <[^>]*> 4549ff79 bc1any4t \$fcc2,0+0000 <text_label>
+0+021c <[^>]*> 00000000 nop
\.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:150: Warning: Condition code register should be even for bc1any2f, was 1
+.*:152: Warning: Condition code register should be even for bc1any2t, was 3
+.*:154: Warning: Condition code register should be 0 or 4 for bc1any4f, was 1
+.*:156: Warning: Condition code register should be 0 or 4 for bc1any4t, was 2
rsqrt2.s $f4, $f8, $f19
rsqrt2.ps $f4, $f8, $f19
+ bc1any2f $fcc1, text_label # warns
+ nop
+ bc1any2t $fcc3, text_label # warns
+ nop
+ bc1any4f $fcc1, text_label # warns
+ nop
+ bc1any4t $fcc2, text_label # warns
+ nop
+
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
#objdump: -dr --prefix-addresses --show-raw-insn -mmips:sb1 -M gpr-names=32
#name: .set arch=FOO
+#stderr: set-arch.l
dump\.o: file format .*mips
--- /dev/null
+.*: Assembler messages:
+.*:146: Warning: Condition code register should be even for c.eq.ps, was 3
+.*:147: Warning: Condition code register should be even for movf.ps, was 3
catch "exec $srcdir/lib/run $AS $ASFLAGS $opts(as) -o dump.o $sourcefile" comp_output
set comp_output [prune_warnings $comp_output]
- if ![string match "" $comp_output] then {
+ if { ![string match "" $comp_output] || $opts(stderr) != "" } then {
if { $opts(stderr) == "" } then {
send_log "$comp_output\n"
verbose "$comp_output" 3