Recent changes added setting of system-wide cache line size and these settings
occur in the top-level configs (se.py and fs.py). This setting also needs to
take place in ruby_fs.py. This change sets the cache line size as appropriate.
Simulation.setWorkCountOptions(system, options)
else:
fatal("incapable of building non-alpha or non-x86 full system!")
+system.cache_line_size = options.cacheline_size
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)