TraceFlag('RefCount')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
- 'InOrderMDU', 'RegDepMap', 'Resource'])
+ 'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
#include "cpu/inorder/resource_pool.hh"
#include "mem/translating_port.hh"
#include "sim/process.hh"
-//#include "sim/root.hh"
#include "sim/stat_control.hh"
#include <algorithm>
cpu_params = params;
resPool = new ResourcePool(this, params);
-// resPool->init();
coreType = "default"; // eventually get this from params
}
- /* Use this port to for syscall emulation writes to memory. */
- //Port *mem_port = NULL;
- //TranslatingPort *trans_port = NULL;
-
for (int i = 0; i < numThreads; ++i) {
if (i < params->workload.size()) {
- DPRINTF(InOrderCPU, "Workload[%i] process is %#x",
+ DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
i, this->thread[i]);
this->thread[i] = new Thread(this, i, params->workload[i],
i);
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
- Process* dummy_proc = params->workload[0]; //LiveProcess::createDummy();
+ Process* dummy_proc = params->workload[0];
this->thread[i] = new Thread(this, i, dummy_proc, i);
-
- // Set Up Syscall Emulation Port
- //this->thread[i]->setMemPort(trans_port);
}
// Setup the TC that will serve as the interface to the threads/CPU.
{
DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid);
- //removeThread(tid);
-
removeFromCurrentThreads(tid);
deactivateThread(tid);
}
-void
-InOrderCPU::signalSwitched()
-{
- panic("Unimplemented Function\n.");
-}
-
-
-void
-InOrderCPU::takeOverFrom(BaseCPU *oldCPU)
-{
- panic("Take Over From Another CPU\n.");
-}
-
uint64_t
InOrderCPU::readPC(unsigned tid)
{
}
}
-/*
-
-void
-InOrderCPU::removeAllInsts()
-{
- instList.clear();
-}
-*/
void
InOrderCPU::dumpInsts()
++num;
}
}
-/*
-
-void
-InOrderCPU::wakeDependents(DynInstPtr &inst)
-{
- iew.wakeDependents(inst);
-}
-*/
void
InOrderCPU::wakeCPU()
DPRINTF(Activity, "Waking up CPU\n");
+ //@todo: figure out how to count idleCycles correctly
//idleCycles += (curTick - 1) - lastRunningCycle;
mainEventQueue.schedule(&tickEvent, curTick);
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
/** The Register File for the CPU */
- /** @TODO: This regFile wont be a sufficient solution for out-of-order, add register
- * files as a resource in order to handle ths problem
- */
TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
TheISA::MiscRegFile miscRegFile;
void switchToActive(int stage_idx)
{ /*pipelineStage[stage_idx]->switchToActive();*/ }
- /** Switches out this CPU. (Unused currently) */
- //void switchOut(Sampler *sampler);
-
- /** Signals to this CPU that a stage has completed switching out. (Unused currently)*/
- void signalSwitched();
-
- /** Takes over from another CPU. (Unused currently)*/
- void takeOverFrom(BaseCPU *oldCPU);
-
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq(unsigned tid)
{ return globalSeqNum[tid]++; }
globalSeqNum[tid] = seq_num;
}
+ /** Get & Update Next Event Number */
InstSeqNum getNextEventNum()
{
return cpuEventNum++;
/** Sets the next NPC of a specific thread. */
void setNextNPC(uint64_t val, unsigned tid);
- /** Add Destination Register To Dependency Maps */
- //void addToRegDepMap(DynInstPtr &inst);
-
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
*/
*/
std::queue<Event*> cpuEventRemoveList;
-#ifdef DEBUG
- /** Debug structure to keep track of the sequence numbers still in
- * flight.
- */
- std::set<InstSeqNum> snList;
-#endif
-
/** Records if instructions need to be removed this cycle due to
* being retired or squashed.
*/
unsigned readStCondFailures() { return stCondFails; }
unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
- public:
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(unsigned tid = 0)
{
/** Pointer to the icache interface. */
MemInterface *icacheInterface;
+
/** Pointer to the dcache interface. */
MemInterface *dcacheInterface;
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "cpu/inorder/cpu.hh"
-//#include "cpu/inorder/params.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "params/InOrderCPU.hh"
DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
threadNumber, seqNum, instcount);
-
-#ifdef DEBUG
- cpu->snList.insert(seqNum);
-#endif
}
DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
threadNumber, seqNum, instcount);
-#ifdef DEBUG
- cpu->snList.erase(seqNum);
-#endif
}
void
void
InOrderDynInst::prefetch(Addr addr, unsigned flags)
{
- // This is the "functional" implementation of prefetch. Not much
- // happens here since prefetches don't affect the architectural
- // state.
-/*
- // Generate a MemReq so we can translate the effective address.
- MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
- req->asid = asid;
-
- // Prefetches never cause faults.
- fault = NoFault;
-
- // note this is a local, not InOrderDynInst::fault
- Fault trans_fault = cpu->translateDataReadReq(req);
-
- if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
- // It's a valid address to cacheable space. Record key MemReq
- // parameters so we can generate another one just like it for
- // the timing access without calling translate() again (which
- // might mess up the TLB).
- effAddr = req->vaddr;
- physEffAddr = req->paddr;
- memReqFlags = req->flags;
- } else {
- // Bogus address (invalid or uncacheable space). Mark it by
- // setting the eff_addr to InvalidAddr.
- effAddr = physEffAddr = MemReq::inval_addr;
- }
-
- if (traceData) {
- traceData->setAddr(addr);
- }
-*/
+ panic("Prefetch Unimplemented\n");
}
void
InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
{
- // Not currently supported.
+ panic("Write-Hint Unimplemented\n");
}
/**
my_hash_t thishash;
#endif
-
-#ifdef DEBUG
-
-void
-InOrderDynInst::dumpSNList()
-{
- std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
-
- int count = 0;
- while (sn_it != cpu->snList.end()) {
- cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
- count++;
- sn_it++;
- }
-}
-#endif
-
/** Count of total number of dynamic instructions. */
static int instcount;
-#ifdef DEBUG
- void dumpSNList();
-#endif
-
/** Dumps out contents of this BaseDynInst. */
void dump();
};
-#endif // __CPU_O3_CPU_INORDER_PARAMS_HH__
+#endif // _CPU_INORDER_PARAMS_HH__
PipelineStage::switchOut()
{
// Stage can immediately switch out.
- cpu->signalSwitched();
+ panic("Switching Out of Stages Unimplemented");
}
DPRINTF(InOrderStage, "\n\n");
}
-bool
-PipelineStage::outOfOrderValid()
-{
- //@TODO: Define this function when OOO is valid
- return false;
-}
-
void
PipelineStage::setResStall(ResReqPtr res_req, unsigned tid)
{
// Don't let instruction pass to next stage if it hasnt completed
// all of it's requests for this stage.
- if (!last_req_completed && !outOfOrderValid())
+ if (!last_req_completed)
continue;
// Send to Next Stage or Break Loop
void
PipelineStage::dumpInsts()
{
- std::cerr << "Insts in Stage " << stageNum << " skidbuffers:" << endl;
+ cprintf("Insts in Stage %i skidbuffers\n",stageNum);
for (int tid=0; tid < ThePipeline::MaxThreads; tid++) {
*/
virtual void tick();
- /** Is out of order processing valid? */
- bool outOfOrderValid();
-
/** Set a resource stall in the pipeline-stage */
void setResStall(ResReqPtr res_req, unsigned tid);
#include "arch/isa_traits.hh"
#include "cpu/base.hh"
-//#include "cpu/inorder/params.hh"
#include "params/InOrderCPU.hh"
if (lhs->stageNum > rhs->stageNum) {
return true;
} else if (lhs->stageNum == rhs->stageNum) {
- /*if (lhs->resNum > rhs->resNum) {
- return true;
- } else {
- return false;
- }*/
-
if (lhs->priority > rhs->priority) {
return true;
} else {
virtual void init();
virtual void initSlots();
- /** Tasks to perform when simulation starts */
- //virtual void startup() { }
-
/** Register Stats for this resource */
virtual void regStats();
findRequest(cache_pkt->cacheReq->getInst()));
assert(cache_req);
-#if TRACING_ON
+
// Get resource request info
+ // @todo: SMT needs to figure out where to get thread # from.
unsigned tid = 0;
-#endif
-
- //tid = pkt->req->getThreadNum();
unsigned stage_num = cache_req->getStageNum();
DynInstPtr inst = cache_req->inst;
virtual void setStatus(Status new_status)
{ thread->setStatus(new_status); }
- /** Returns a pointer to the last graduated/committed instruction in the thread */
- //DynInstPtr getLastGradInst() { return thread->getLastGradInst(); }
-
/** Set the status to Active. Optional delay indicates number of
* cycles to wait before beginning execution. */
virtual void activate(int delay = 1);
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