pa.md (post_store, pre_load): New expanders.
authorJeffrey A Law <law@cygnus.com>
Wed, 28 Jul 1999 05:21:38 +0000 (05:21 +0000)
committerJeff Law <law@gcc.gnu.org>
Wed, 28 Jul 1999 05:21:38 +0000 (23:21 -0600)
        * pa.md (post_store, pre_load): New expanders.
        (post_stwm, pre_ldwm): Renamed to post_stw and pre_ldw respectively.
        (post_ldwm, pre_stwm): Make these unnamed patterns since we never
        need to directly generate RTL for them.
        * pa.c (hppa_expand_prologue, hppa_expand_epilogue): Corresponding
        changes.

From-SVN: r28307

gcc/ChangeLog
gcc/config/pa/pa.c
gcc/config/pa/pa.md

index f3c4a5a6cee4b0ec831ba3a29465f17c1de86501..65a8941ae675c8bf5c6d2bbcfe7e0ee41cdaa3fc 100644 (file)
@@ -1,3 +1,12 @@
+Tue Jul 27 23:20:21 1999  Jeffrey A Law  (law@cygnus.com)
+
+       * pa.md (post_store, pre_load): New expanders.
+       (post_stwm, pre_ldwm): Renamed to post_stw and pre_ldw respectively.
+       (post_ldwm, pre_stwm): Make these unnamed patterns since we never
+       need to directly generate RTL for them.
+       * pa.c (hppa_expand_prologue, hppa_expand_epilogue): Corresponding
+       changes.
+
 Tue Jul 27 16:05:52 1999  David Edelsohn  <edelsohn@gnu.org>
 
        * aix43.h (ASM_CPU_SPEC, CPP_CPU_SPEC): Add rs64a and PPC630.
index 0293ebe227659f9dcf5c26dc4074b30df9f13187..33efebca79baf1aca6895f4cfb88ea9be8b4f1e2 100644 (file)
@@ -2688,7 +2688,7 @@ hppa_expand_prologue()
        emit_move_insn (tmpreg, frame_pointer_rtx);
        emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
        if (VAL_14_BITS_P (actual_fsize))
-         emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
+         emit_insn (gen_post_store (stack_pointer_rtx, tmpreg, size_rtx));
        else
          {
            /* It is incorrect to store the saved frame pointer at *sp,
@@ -2697,7 +2697,8 @@ hppa_expand_prologue()
               So instead use stwm to store at *sp and post-increment the
               stack pointer as an atomic operation.  Then increment sp to
               finish allocating the new frame.  */
-           emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
+           emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
+                      GEN_INT (64)));
            set_reg_plus_d (STACK_POINTER_REGNUM,
                            STACK_POINTER_REGNUM,
                            actual_fsize - 64);
@@ -2820,9 +2821,9 @@ hppa_expand_prologue()
            if (merge_sp_adjust_with_store)
              {
                merge_sp_adjust_with_store = 0;
-               emit_insn (gen_post_stwm (stack_pointer_rtx,
-                                         gen_rtx_REG (word_mode, i),
-                                         GEN_INT (-offset)));
+               emit_insn (gen_post_store (stack_pointer_rtx,
+                                          gen_rtx_REG (word_mode, i),
+                                          GEN_INT (-offset)));
              }
            else
              store_reg (i, offset, STACK_POINTER_REGNUM);
@@ -3032,13 +3033,13 @@ hppa_expand_epilogue ()
   else if (frame_pointer_needed)
     {
       set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
-      emit_insn (gen_pre_ldwm (frame_pointer_rtx, 
+      emit_insn (gen_pre_load (frame_pointer_rtx, 
                               stack_pointer_rtx,
                               GEN_INT (-64)));
     }
   /* If we were deferring a callee register restore, do it now.  */
   else if (! frame_pointer_needed  && merge_sp_adjust_with_load)
-    emit_insn (gen_pre_ldwm (gen_rtx_REG (word_mode, merge_sp_adjust_with_load),
+    emit_insn (gen_pre_load (gen_rtx_REG (word_mode, merge_sp_adjust_with_load),
                             stack_pointer_rtx,
                             GEN_INT (- actual_fsize)));
   else if (actual_fsize != 0)
index 7d81f06d2b64737549421968d65693710c1e90f4..af209c3d6eec054245b4680e72cb36c38af99463 100644 (file)
 
 ;; Load or store with base-register modification.
 
-(define_insn "pre_ldwm"
+(define_expand "pre_load"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+             (mem (plus (match_operand 1 "register_operand" "")
+                              (match_operand 2 "pre_cint_operand" ""))))
+             (set (match_dup 1)
+                  (plus (match_dup 1) (match_dup 2)))])]
+  ""
+  "
+{
+  emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_insn "pre_ldw"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
                         (match_operand:SI 2 "pre_cint_operand" ""))))
   [(set_attr "type" "load")
    (set_attr "length" "4")])
 
-(define_insn "pre_stwm"
+(define_insn ""
   [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
                         (match_operand:SI 1 "pre_cint_operand" "")))
        (match_operand:SI 2 "reg_or_0_operand" "rM"))
   [(set_attr "type" "store")
    (set_attr "length" "4")])
 
-(define_insn "post_ldwm"
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
        (mem:SI (match_operand:SI 1 "register_operand" "+r")))
    (set (match_dup 1)
   [(set_attr "type" "load")
    (set_attr "length" "4")])
 
-(define_insn "post_stwm"
+(define_expand "post_store"
+  [(parallel [(set (mem (match_operand 0 "register_operand" ""))
+                  (match_operand 1 "reg_or_0_operand" ""))
+             (set (match_dup 0)
+                  (plus (match_dup 0)
+                        (match_operand 2 "post_cint_operand" "")))])]
+  ""
+  "
+{
+  emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_insn "post_stw"
   [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
        (match_operand:SI 1 "reg_or_0_operand" "rM"))
    (set (match_dup 0)