radeonsi: fix maximum advertised point size / line width

The hardware registers store the half-size/width in 12.4 fixed point
format, so 8192 is the maximum.

Fixes dEQP-GLES3.functional.rasterization.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index b327fd106a85ad5fb827dd7f5b8af503c1c77b8c..949d313bb5e4b2d8fc551448ee365a25b2dd1ffb 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1004,17 +1004,12 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
 static float r600_get_paramf(struct pipe_screen* pscreen,
                             enum pipe_capf param)
 {
-       struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
-
        switch (param) {
        case PIPE_CAPF_MAX_LINE_WIDTH:
        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
        case PIPE_CAPF_MAX_POINT_WIDTH:
        case PIPE_CAPF_MAX_POINT_WIDTH_AA:
-               if (rscreen->family >= CHIP_CEDAR)
-                       return 16384.0f;
-               else
-                       return 8192.0f;
+               return 8192.0f;
        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
                return 16.0f;
        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e82ca6a69464f3840268c1300d53ca5228f74c58..3fbacec5668e7b7468577b28f2f56e5a7998e821 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -902,8 +902,8 @@ static void *si_create_rs_state(struct pipe_context *ctx,
                        S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
                        S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
 
-       tmp = (unsigned)state->line_width * 8;
-       si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
+       si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
+                      S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
        si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
                       S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
                       S_028A48_MSAA_ENABLE(state->multisample ||