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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 7f12567fea5f79cb337d783435bcdaaea7ee2e6d..542fac162028bc7a3e239ee4e44db2f51b3cbd85 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -83,3 +83,12 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 | n/a     | Saturating Shift left logical       | VSLL (r2 <= rt,ra,rb <= r15), mm=01|
 | n/a     | Saturating Shift left logical imm   | VSLLI (r2 <= rt,ra <= r15), mm=01|
 
+## 16-bit Comparison
+
+| Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
+| ------------------   | ------------------------- | ------------------- |
+| CMPEQ16 rt, ra, rb   | Compare equal             | VSEQ (r16 <= rt,ra,rb <= r29), mm=00|
+| SCMPLT16 rt, ra, rb   | Signed Compare less than        | !VSGT (r16 <= rt,ra,rb <= r23), mm=00|
+| SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (r16 <= rt,ra,rb <= r23), mm=00|
+| UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (r24 <= rt,ra,rb <= r29), mm=00|
+| UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (r24 <= rt,ra,rb <= r29), mm=00|