soc/interconnect/stream/: add busy signal to PipelinedActor

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 63f4c1f68d9653108f81c848233a73439f9d7108..eac396c2d66d0fc50ebb56ad5b7c93e39f739ed0 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -390,19 +390,23 @@ class PipelinedActor(BinaryActor):
     def __init__(self, latency):
         self.latency = latency
         self.pipe_ce = Signal()
+        self.busy = Signal()
         BinaryActor.__init__(self, latency)
 
     def build_binary_control(self, sink, source, latency):
+        busy = 0
         valid = sink.valid
         for i in range(latency):
             valid_n = Signal()
             self.sync += If(self.pipe_ce, valid_n.eq(valid))
             valid = valid_n
+            busy = busy | valid
 
         self.comb += [
             self.pipe_ce.eq(source.ready | ~valid),
             sink.ready.eq(self.pipe_ce),
-            source.valid.eq(valid)
+            source.valid.eq(valid),
+            self.busy.eq(busy)
         ]
         last = sink.valid & sink.last
         for i in range(latency):