x86: don't use opcode_length to identify pseudo prefixes

This is in preparation of opcode_length going away as a field in the
templates. Identify pseudo prefixes by a base opcode of zero instead:
No real prefix has an opcode of zero. This at the same time allows
dropping a curious special case from i386-gen.

Since most attributes are identical for all pseudo prefixes, take the
opportunity and also template them.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19c47b762865d3ca4e0a7abd801d61fdb04bf0e6..91a8ad04324702c84b33a6db0f3c75add22ec071 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-24  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (parse_insn): Recognize pseudo prefixes by
+       base_opcode and extension_opcode.
+
 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (pte): Re-order opc_pfx[] entries.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 1f2e4079af1e0fa1e37f603fe359be78be2f81ca..dfb64d44f8b732c88eb1212ca4f772c092bb34b7 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5101,10 +5101,11 @@ parse_insn (char *line, char *mnemonic)
                      current_templates->start->name);
              return NULL;
            }
-         if (current_templates->start->opcode_length == 0)
+
+         if (current_templates->start->base_opcode == PSEUDO_PREFIX)
            {
              /* Handle pseudo prefixes.  */
-             switch (current_templates->start->base_opcode)
+             switch (current_templates->start->extension_opcode)
                {
                case Prefix_Disp8:
                  /* {disp8} */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 524057e64107f64c515f4e490aa4f290b8073575..cb7bdabf7525dd5b2ca1f015009ab5dffd4bfa32 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2021-03-24  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
+       check.
+       * i386-opc.h (Prefix_*): Move #define-s.
+       * i386-opc.tbl: Move pseudo prefix enumerator values to
+       extension opcode field. Introduce pseudopfx template.
+       * i386-tbl.h: Re-generate.
+
 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend

diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 10861b6bda3a46d98b48e88fe8e2f1b10a9c5b10..2f4caba365ed937bbace042a24c088c95a3e9348 100644 (file)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1209,8 +1209,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, char **opnd, int lineno)
                       || strncasecmp(str, "EVex=", 5) == 0
                       || strncasecmp(str, "Disp8MemShift=", 14) == 0
                       || strncasecmp(str, "Masking=", 8) == 0
-                      || strcasecmp(str, "SAE") == 0
-                      || strcasecmp(str, "IsPrefix") == 0)
+                      || strcasecmp(str, "SAE") == 0)
                regular_encoding = 0;
 
              set_bitfield (str, modifiers, val, ARRAY_SIZE (modifiers),

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0fe0be615e0e9ba3193f511915193cec8ce31ac4..ad4a525484f0d1eeefafe2b91a3bf3abaf70cd02 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -926,6 +926,17 @@ typedef struct insn_template
 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
+/* (Fake) base opcode value for pseudo prefixes.  */
+#define PSEUDO_PREFIX 0
+
+  /* extension_opcode is the 3 bit extension for group <n> insns.
+     This field is also used to store the 8-bit opcode suffix for the
+     AMD 3DNow! instructions.
+     If this template has no extension opcode (the usual case) use None
+     Instructions */
+  unsigned short extension_opcode;
+#define None 0xffff            /* If no extension_opcode is possible.  */
+
 /* Pseudo prefixes.  */
 #define Prefix_Disp8           0       /* {disp8} */
 #define Prefix_Disp16          1       /* {disp16} */
@@ -938,14 +949,6 @@ typedef struct insn_template
 #define Prefix_REX             8       /* {rex} */
 #define Prefix_NoOptimize      9       /* {nooptimize} */
 
-  /* extension_opcode is the 3 bit extension for group <n> insns.
-     This field is also used to store the 8-bit opcode suffix for the
-     AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None
-     Instructions */
-  unsigned short extension_opcode;
-#define None 0xffff            /* If no extension_opcode is possible.  */
-
   /* Opcode length.  */
   unsigned char opcode_length;
 

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 7d0ec3c1f3c23bfb25cd3ca433025b96dae6fa97..493355f9b5499c489658b9f7147747d2dd3a20a0 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -856,19 +856,14 @@ rex.wrb, 0x4d, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|
 rex.wrx, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 rex.wrxb, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 
-// Pseudo prefixes (opcode_length == 0)
-
-{disp8}, Prefix_Disp8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{disp16}, Prefix_Disp16, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{disp32}, Prefix_Disp32, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{load}, Prefix_Load, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{store}, Prefix_Store, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{vex}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{vex2}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{vex3}, Prefix_VEX3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{evex}, Prefix_EVEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{rex}, Prefix_REX, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
-{nooptimize}, Prefix_NoOptimize, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
+// Pseudo prefixes (base_opcode == PSEUDO_PREFIX)
+
+<pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, \
+                      load:Load:0, store:Store:0, \
+                      vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, \
+                      rex:REX:Cpu64, nooptimize:NoOptimize:0>
+
+{<pseudopfx>}, PSEUDO_PREFIX, Prefix_<pseudopfx:ident>, 0, <pseudopfx:cpu>, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 
 // 486 extensions.
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index a59c764ce03373e29af6a910da128a1cfa52d33f..735401fe79125cb760ca1aea22afe5aa7a39664a 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -8184,7 +8184,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 1, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{disp8}", 0, None, 0, 0,
+  { "{disp8}", 0, Prefix_Disp8, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8197,7 +8197,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{disp16}", 1, None, 0, 0,
+  { "{disp16}", 0, Prefix_Disp16, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8210,7 +8210,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{disp32}", 2, None, 0, 0,
+  { "{disp32}", 0, Prefix_Disp32, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8223,7 +8223,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{load}", 3, None, 0, 0,
+  { "{load}", 0, Prefix_Load, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8236,7 +8236,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{store}", 4, None, 0, 0,
+  { "{store}", 0, Prefix_Store, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8249,7 +8249,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex}", 5, None, 0, 0,
+  { "{vex}", 0, Prefix_VEX, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8262,7 +8262,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex2}", 5, None, 0, 0,
+  { "{vex2}", 0, Prefix_VEX, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8275,7 +8275,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex3}", 6, None, 0, 0,
+  { "{vex3}", 0, Prefix_VEX3, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8288,7 +8288,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{evex}", 7, None, 0, 0,
+  { "{evex}", 0, Prefix_EVEX, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8301,7 +8301,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{rex}", 8, None, 0, 0,
+  { "{rex}", 0, Prefix_REX, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
@@ -8314,7 +8314,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 1, 0, 0 } },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{nooptimize}", 9, None, 0, 0,
+  { "{nooptimize}", 0, Prefix_NoOptimize, 0, 0,
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },