}
+std::string
+IntConcatShiftOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printSecondSrc = true;
+ bool printShift = false;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (!myMnemonic.compare("sradi") ||
+ !myMnemonic.compare("extswsli")) {
+ printSecondSrc = false;
+ printShift = true;
+ }
+
+ // Additional characters depending on isa bits being set
+ if (rcSet) myMnemonic = myMnemonic + ".";
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+
+ // Print the first destination only
+ if (_numDestRegs > 0) {
+ printReg(ss, destRegIdx(0));
+ }
+
+ // Print the first source register
+ if (_numSrcRegs > 0) {
+ if (_numDestRegs > 0) {
+ ss << ", ";
+ }
+ printReg(ss, srcRegIdx(0));
+
+ // Print the second source register
+ if (printSecondSrc) {
+
+ // If the instruction updates the CR, the destination register
+ // Ra is read and thus, it becomes the second source register
+ // due to its higher precedence over Rb. In this case, it must
+ // be skipped.
+ if (rcSet) {
+ if (_numSrcRegs > 2) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(2));
+ }
+ } else {
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+ }
+ }
+ }
+
+ // Print the shift value
+ if (printShift) {
+ ss << ", " << shift;
+ }
+
+ return ss.str();
+}
+
+
std::string
IntRotateOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
};
+/**
+ * Class for integer shift operations with a shift value obtained from
+ * a register or by concatenating immediates.
+ */
+class IntConcatShiftOp : public IntOp
+{
+ protected:
+
+ uint32_t shift;
+
+ /// Constructor
+ IntConcatShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass),
+ shift(((uint32_t)machInst.shn << 5) | machInst.sh)
+ {
+ }
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
+};
+
+
/**
* Class for integer rotate operations.
*/
true);
}
+ format IntConcatShiftOp {
+ 27: sld({{
+ int64_t shift = Rb_sd;
+ uint64_t res = Rs & ~((shift << 57) >> 63);
+ if (shift != 0) {
+ shift = shift & 0x3f;
+ res = res << shift;
+ }
+ Ra = res;
+ }});
+
+ 539: srd({{
+ int64_t shift = Rb_sd;
+ uint64_t res = Rs & ~((shift << 57) >> 63);
+ if (shift != 0) {
+ shift = shift & 0x3f;
+ res = res >> shift;
+ }
+ Ra = res;
+ }});
+
+ 794: srad({{
+ int64_t src = Rs_sd;
+ uint64_t shift = Rb;
+ int64_t res;
+ if ((shift & 0x40) != 0) {
+ res = src >> 63;
+ if (res != 0) {
+ setCA = true;
+ }
+ } else {
+ if (shift != 0) {
+ shift = shift & 0x3f;
+ res = src >> shift;
+ if (src < 0 && (src & mask(shift)) != 0) {
+ setCA = true;
+ }
+ } else {
+ res = src;
+ }
+ }
+ Ra = res;
+ }},
+ true);
+ }
+
format StoreIndexOp {
663: stfsx({{ Mem_sf = Fs_sf; }});
727: stfdx({{ Mem_df = Fs; }});
true);
}
- default: decode XFX_XO {
- format IntOp {
- 339: decode SPR {
- 0x20: mfxer({{ Rt = XER; }});
- 0x100: mflr({{ Rt = LR; }});
- 0x120: mfctr({{ Rt = CTR; }});
- 0x1f9: mftar({{ Rt = TAR; }});
- }
-
- 467: decode SPR {
- 0x20: mtxer({{ XER = Rs; }});
- 0x100: mtlr({{ LR = Rs; }});
- 0x120: mtctr({{ CTR = Rs; }});
- 0x1f9: mttar({{ TAR = Rs; }});
- }
-
- 144: mtcrf({{
- uint32_t mask = 0;
- for (int i = 0; i < 8; ++i) {
- if (((FXM >> i) & 0x1) == 0x1) {
- mask |= 0xf << (4 * i);
+ // These instructions are of XS form and use bits 21 - 29 as XO.
+ default: decode XS_XO {
+ format IntConcatShiftOp {
+ 413: sradi({{
+ int64_t src = Rs_sd;
+ if (shift != 0) {
+ Ra = src >> shift;
+ if (src < 0 && (src & mask(shift))) {
+ setCA = true;
}
+ } else {
+ Ra = src;
+ }
+ }},
+ true);
+
+ 445: extswsli({{
+ int64_t src = Rs_sw;
+ if (shift != 0) {
+ Ra = src << shift;
+ } else {
+ Ra = src;
}
- CR = (Rs & mask) | (CR & ~mask);
}});
+ }
+
+ default: decode XFX_XO {
+ format IntOp {
+ 339: decode SPR {
+ 0x20: mfxer({{ Rt = XER; }});
+ 0x100: mflr({{ Rt = LR; }});
+ 0x120: mfctr({{ Rt = CTR; }});
+ 0x1f9: mftar({{ Rt = TAR; }});
+ }
- 19: mfcr({{ Rt = CR; }});
+ 467: decode SPR {
+ 0x20: mtxer({{ XER = Rs; }});
+ 0x100: mtlr({{ LR = Rs; }});
+ 0x120: mtctr({{ CTR = Rs; }});
+ 0x1f9: mttar({{ TAR = Rs; }});
+ }
- 512: mcrxr({{
- CR = insertCRField(CR, BF, XER<31:28>);
- XER = XER<27:0>;
- }});
+ 144: mtcrf({{
+ uint32_t mask = 0;
+ for (int i = 0; i < 8; ++i) {
+ if (((FXM >> i) & 0x1) == 0x1) {
+ mask |= 0xf << (4 * i);
+ }
+ }
+ CR = (Rs & mask) | (CR & ~mask);
+ }});
+
+ 19: mfcr({{ Rt = CR; }});
+
+ 512: mcrxr({{
+ CR = insertCRField(CR, BF, XER<31:28>);
+ XER = XER<27:0>;
+ }});
+ }
}
}
}
}};
+// Integer instructions that also perform shift operations. Everything
+// is same as above except if the shift value is not obtained from a
+// register, two immediates need to be concatenated to get the final
+// shift value.
+def format IntConcatShiftOp(code, computeCA = 0, inst_flags = []) {{
+ dict = {'result':'Ra'}
+
+ # Add code to setup variables and access XER if necessary
+ code = 'M5_VAR_USED bool setCA = false;\n' + code
+
+ # Code when Rc is set
+ code_rc1 = readXERCode + code + computeCR0Code % dict
+
+ # Add code for calculating the carry, if needed
+ if computeCA:
+ code = readXERCode + code + setCACode + setXERCode
+ code_rc1 += setCACode + setXERCode
+
+ # Generate the first class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntConcatShiftOp', code, inst_flags,
+ CheckRcDecode, BasicConstructor)
+
+ # Generate the second class
+ (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \
+ GenAluOp(name, Name + 'RcSet', 'IntConcatShiftOp', code_rc1,
+ inst_flags, CheckRcDecode, IntRcConstructor)
+
+ # Finally, add to the other outputs
+ header_output += header_output_rc1
+ decoder_output += decoder_output_rc1
+ exec_output += exec_output_rc1
+}};
+
+
// A special format for rotate instructions which use certain fields
// from the instruction's binary encoding. We need two versions for each
// instruction to deal with the Rc bit.
projects / gem5.git / commitdiff