r300: Added the PVS_OP_DST_OPERAND documentation from AMD.

diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 338782e6b0c4617de48b755c73f833debb5f8e80..041ba85665b8545a999900ba4ee86efafc48c438 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -2504,6 +2504,45 @@ enum {
        PVS_SRC_SELECT_FORCE_1          = 5,    /* Force Component to 1.0 */
 };
 
+/* PVS Opcode & Destination Operand Description */
+
+enum {
+       PVS_DST_OPCODE_MASK             = 0x3f,
+       PVS_DST_OPCODE_SHIFT            = 0,
+       PVS_DST_MATH_INST_MASK          = 0x1,
+       PVS_DST_MATH_INST_SHIFT         = 6,
+       PVS_DST_MACRO_INST_MASK         = 0x1,
+       PVS_DST_MACRO_INST_SHIFT        = 7,
+       PVS_DST_REG_TYPE_MASK           = 0xf,
+       PVS_DST_REG_TYPE_SHIFT          = 8,
+       PVS_DST_ADDR_MODE_1_MASK        = 0x1,
+       PVS_DST_ADDR_MODE_1_SHIFT       = 12,
+       PVS_DST_OFFSET_MASK             = 0x7f,
+       PVS_DST_OFFSET_SHIFT            = 13,
+       PVS_DST_WE_X_MASK               = 0x1,
+       PVS_DST_WE_X_SHIFT              = 20,
+       PVS_DST_WE_Y_MASK               = 0x1,
+       PVS_DST_WE_Y_SHIFT              = 21,
+       PVS_DST_WE_Z_MASK               = 0x1,
+       PVS_DST_WE_Z_SHIFT              = 22,
+       PVS_DST_WE_W_MASK               = 0x1,
+       PVS_DST_WE_W_SHIFT              = 23,
+       PVS_DST_VE_SAT_MASK             = 0x1,
+       PVS_DST_VE_SAT_SHIFT            = 24,
+       PVS_DST_ME_SAT_MASK             = 0x1,
+       PVS_DST_ME_SAT_SHIFT            = 25,
+       PVS_DST_PRED_ENABLE_MASK        = 0x1,
+       PVS_DST_PRED_ENABLE_SHIFT       = 26,
+       PVS_DST_PRED_SENSE_MASK         = 0x1,
+       PVS_DST_PRED_SENSE_SHIFT        = 27,
+       PVS_DST_DUAL_MATH_OP_MASK       = 0x3,
+       PVS_DST_DUAL_MATH_OP_SHIFT      = 27,
+       PVS_DST_ADDR_SEL_MASK           = 0x3,
+       PVS_DST_ADDR_SEL_SHIFT          = 29,
+       PVS_DST_ADDR_MODE_0_MASK        = 0x1,
+       PVS_DST_ADDR_MODE_0_SHIFT       = 31,
+};
+
 /*\}*/
 
 /* BEGIN: Packet 3 commands */

diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.h b/src/mesa/drivers/dri/r300/r300_vertprog.h
index 5727449bc098d6e288d88716f9e50346a091dc9a..61da603371e8a01af2d2ace64d414d1351a49e6f 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_vertprog.h
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.h
@@ -3,17 +3,6 @@
 
 #include "r300_reg.h"
 
-/* TODO: get documentation from AMD for these... */
-
-#define R300_VPI_OUT_REG_INDEX_SHIFT            13
-       /* GUESS based on fglrx native limits */
-#define R300_VPI_OUT_REG_INDEX_MASK             (31 << 13)
-
-#define R300_VPI_OUT_WRITE_X                    (1 << 20)
-#define R300_VPI_OUT_WRITE_Y                    (1 << 21)
-#define R300_VPI_OUT_WRITE_Z                    (1 << 22)
-#define R300_VPI_OUT_WRITE_W                    (1 << 23)
-
 #define R300_VPI_IN_REG_INDEX_SHIFT             5
        /* GUESS based on fglrx native limits */
 #define R300_VPI_IN_REG_INDEX_MASK              (255 << 5)
@@ -29,17 +18,18 @@
 #define R300_VPI_IN_NEG_W                       (1 << 28)
 
 #define PVS_VECTOR_OPCODE(opcode, reg_index, reg_writemask, reg_class) \
-       ((opcode)                                                       \
-        | ((reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT)                \
-        | ((reg_writemask) << 20)                                      \
-        | ((reg_class) << 8))
+        (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT)      \
+        | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT)  \
+        | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT)        /* X Y Z W */   \
+        | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT))
 
 #define PVS_MATH_OPCODE(opcode, reg_index, reg_writemask, reg_class)   \
-       ((opcode)                                                       \
-        | (1 << 6)     /* FIXME: PVS_DST_MATH_INST */                  \
-        | ((reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT)                \
-        | ((reg_writemask) << 20)                                      \
-        | ((reg_class) << 8))
+        (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT)      \
+        | ((1 & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT)    \
+        | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT)  \
+        | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT)        /* X Y Z W */   \
+        | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT))
+
 
 #define PVS_SOURCE_OPCODE(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate)     \
        (((in_reg_index) << R300_VPI_IN_REG_INDEX_SHIFT)                                        \
@@ -60,6 +50,11 @@
 #define VSF_FLAG_ALL  0xf
 #define VSF_FLAG_NONE  0
 
+#define R300_VPI_OUT_WRITE_X                    (1 << 20)
+#define R300_VPI_OUT_WRITE_Y                    (1 << 21)
+#define R300_VPI_OUT_WRITE_Z                    (1 << 22)
+#define R300_VPI_OUT_WRITE_W                    (1 << 23)
+
 #define VP_OUTMASK_X   R300_VPI_OUT_WRITE_X
 #define VP_OUTMASK_Y   R300_VPI_OUT_WRITE_Y
 #define VP_OUTMASK_Z   R300_VPI_OUT_WRITE_Z
@@ -78,8 +73,8 @@
 
 #define VP_OUT(instr,outclass,outidx,outmask) \
        (VE_##instr |                           \
-       ((outidx) << R300_VPI_OUT_REG_INDEX_SHIFT) |            \
-       (PVS_DST_REG_##outclass << 8) |         \
+       ((outidx & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) |              \
+       ((PVS_DST_REG_##outclass & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT) |          \
        VP_OUTMASK_##outmask)
 
 #define VP_IN(inclass,inidx) \