// Fields for FPSCR manipulation instructions
def bitfield FLM <24:17>;
-def bitfield L <25>;
-def bitfield W <16>;
+// Named so to avoid conflicts with potential template typenames
+def bitfield L_FIELD <25>;
+// Named so to avoid conflicts with range_map.hh
+def bitfield W_FIELD <16>;
// Named so to avoid conflicts with range.hh
def bitfield U_FIELD <15:12>;
}});
583: mffs({{ Ft_uq = FPSCR; }});
134: mtfsfi({{
- FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD);
+ FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
+ U_FIELD);
}});
711: mtfsf({{
- if (L == 1) { FPSCR = Fb_uq; }
+ if (L_FIELD == 1) { FPSCR = Fb_uq; }
else {
for (int i = 0; i < 8; ++i) {
if (bits(FLM, i) == 1) {
- int k = 4 * (i + (8 * (1 - W)));
+ int k = 4 * (i + (8 * (1 - W_FIELD)));
FPSCR = insertBits(FPSCR, k, k + 3,
bits(Fb_uq, k, k + 3));
}