Add YOSYS to the implicitly defined verilog macros in verific

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 2c28585144654e64183b048c2949a344919b2945..d5574f95adfbf2de50201ea2a6d4f58de68dfec7 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2295,7 +2295,7 @@ struct VerificPass : public Pass {
                log("\n");
                log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
                log("the language version (and before file names) to set additional verilog defines.\n");
-               log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
+               log("The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly.\n");
                log("\n");
                log("\n");
                log("    verific -formal <verilog-file>..\n");
@@ -2713,6 +2713,7 @@ struct VerificPass : public Pass {
                        else
                                log_abort();
 
+                       veri_file::DefineMacro("YOSYS");
                        veri_file::DefineMacro("VERIFIC");
                        veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");