if piobus != None:
cpu_seq.pio_port = piobus.slave
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
L2cacheMemory = l2_cache,
ruby_system = ruby_system)
- exec("system.l2_cntrl%d = l2_cntrl" % i)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
memBuffer = mem_cntrl,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
if piobus != None:
cpu_seq.pio_port = piobus.slave
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
memBuffer = mem_cntrl,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
if piobus != None:
cpu_seq.pio_port = piobus.slave
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
L2cacheMemory = l2_cache,
ruby_system = ruby_system)
- exec("system.l2_cntrl%d = l2_cntrl" % i)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
memBuffer = mem_cntrl,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
if piobus != None:
cpu_seq.pio_port = piobus.slave
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
N_tokens = n_tokens,
ruby_system = ruby_system)
- exec("system.l2_cntrl%d = l2_cntrl" % i)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
l2_select_num_bits = l2_bits,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
if options.recycle_latency:
dir_cntrl.recycle_latency = options.recycle_latency
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:
if piobus != None:
cpu_seq.pio_port = piobus.slave
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
memBuffer = mem_cntrl,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1