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Make the fsr a serializing register. Other control registers probably need this as...
authorGabe Black <gblack@eecs.umich.edu>
Sat, 14 Apr 2007 17:07:24 +0000 (17:07 +0000)
committerGabe Black <gblack@eecs.umich.edu>
Sat, 14 Apr 2007 17:07:24 +0000 (17:07 +0000)
--HG--
extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6

src/arch/sparc/isa/operands.isa patch | blob | history

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 58d616a7a20d9f30a56d84e2eb8a333b9eb56aa5..110b37d1535d8a1d09f64c651086f79b2b2da715 100644 (file)
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -187,7 +187,7 @@ def operands {{
     'Hver':            ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
     'StrandStsReg':    ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
 
-    'Fsr':             ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
+    'Fsr':             ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
     # Mem gets a large number so it's always last
     'Mem':             ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)