Add section to HDL_workflow/coriolis2 documenting how to use soclayou

repo

diff --git a/HDL_workflow/coriolis2.mdwn b/HDL_workflow/coriolis2.mdwn
index fd37cc0550015a654a07047f08b65bfef31519ff..71cade77782f6e51b5199de14fdf436fc60f3322 100644 (file)
--- a/HDL_workflow/coriolis2.mdwn
+++ b/HDL_workflow/coriolis2.mdwn
@@ -287,13 +287,35 @@ You also have a third repository for various blocks/chip/examples here:
 
 (with a basic doc under "doc/"...)
 
-# Check out the libresoc "soclayout" repository
-
-See [[HDL_workflow]] for git clone instructions
-
-    $ git clone ssh://gitolite3@git.libre-riscv.org:922/libresoc.git
-
-TODO further, here.
+# Clone "soclayout" repository and place and route a layout experiment
+
+In order to do the physical layout of the logical 
+netlists generated by yosys we use coriolis and 
+alliace installed above by doing the following 
+(using experiment9 as an example):
+
+    $ cd ~/src
+    $ git clone https://git.libre-soc.org/git/soclayout.git
+    $ cd soclayout/
+    $ find . -type f -exec sed -i 's/'lkcl'/'"$USER"'/g' {} \;
+    $ ./mksym.sh
+    $ cd experiments9
+    $ ./mksym.sh
+    $ yosys
+    yosys> read_ilang test_issuer.il
+    yosys> heirarchy -check -top test_issuer
+    yosys> synth -top test_issuer
+    yosys> dfflibmap -liberty /home/USERNAME/alliance/install/cells/sxlib/sxlib.lib
+    yosys> abc -liberty /home/USERNAME/alliance/install/cells/sxlib/sxlib.lib
+    yosys> clean
+    yosys> write_blif test_issuer.blif
+    yosys> exit
+    $ make layout (will take between 20min and 2 hours depending on your hardware)
+    $ make view
+
+A window should open with with contents that look like this (pretty isn't it?)
+
+[[!img 180nm_Oct2020/2020-07-03_11-04.png ]]
 
 # Issues running from (e.g.) archlinux as host and debian as a chroot