[aarch64] Adjust Falkor's sign extend reg+reg address cost

Adjust Falkor's register_sextend cost from 4 to 3.  This fixes a testsuite
failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating
a sbfiz instruction rather than a load with sign extension.

No performance changes.

gcc/ChangeLog:

2018-08-08  Luis Machado  <luis.machado@linaro.org>

	* config/aarch64/aarch64.c (qdf24xx_addrcost_table)
	<register_sextend>: Set to 3.

From-SVN: r263388

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 15baa0ce53d704ed981085ff4478bcb010edbd0d..0f6e466fd98c7a2f82e667bd51a81833505871d4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-08-08  Luis Machado  <luis.machado@linaro.org>
+
+       * config/aarch64/aarch64.c (qdf24xx_addrcost_table)
+       <register_sextend>: Set to 3.
+
 2018-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        PR target/86838

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 13b5448aca88555222481f0955237b6fdcbb38b9..1c470cb3d4ff02ce4b70f5f0319ca8afa61c2261 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -329,7 +329,7 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table =
   1, /* pre_modify  */
   1, /* post_modify  */
   3, /* register_offset  */
-  4, /* register_sextend  */
+  3, /* register_sextend  */
   3, /* register_zextend  */
   2, /* imm_offset  */
 };