Add the m5 parameter to the ns83820 device model so that we

can pass simulator specific options to the device driver.

dev/ns_gige.cc:
    Add the m5 register and parameter to the ns83820 device model
    so that we can pass simulator specific options to the device
    driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
    Add the m5 register to the ns83820 device model

--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 47631642cdfb565039fb23fa2acf37869a1bac5a..7560b199499230a2ec795fd4dda200bb3f1c15b9 100644 (file)
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -747,6 +747,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
                 reg = regs.tesr;
                 break;
 
+              case M5REG:
+                reg = params()->m5reg;
+                break;
+
               default:
                 panic("reading unimplemented register: addr=%#x", daddr);
             }
@@ -2708,6 +2712,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<uint32_t> pci_func;
     Param<uint32_t> tx_fifo_size;
     Param<uint32_t> rx_fifo_size;
+    Param<uint32_t> m5reg;
 
 END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -2740,7 +2745,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
     INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
-    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072)
+    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072),
+    INIT_PARAM(m5reg, "m5 register")
 
 END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -2777,6 +2783,7 @@ CREATE_SIM_OBJECT(NSGigE)
     params->eaddr = hardware_address;
     params->tx_fifo_size = tx_fifo_size;
     params->rx_fifo_size = rx_fifo_size;
+    params->m5reg = m5reg;
     return new NSGigE(params);
 }
 

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 544a300c3d137904ec8d9deadc0fb524be038cb4..357f082536fdd160b90616e07bb385fde3414b00 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -343,6 +343,7 @@ class NSGigE : public PciDev
         Net::EthAddr eaddr;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_size;
+        uint32_t m5reg;
     };
 
     NSGigE(Params *params);

diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h
index 01577fa398438a86a4bbd615a24769c1feb81089..ab983378825fd738cb188724637e937684517315 100644 (file)
--- a/dev/ns_gige_reg.h
+++ b/dev/ns_gige_reg.h
@@ -117,7 +117,8 @@
 #define TANLPAR                0xec
 #define TANER          0xf0
 #define TESR           0xf4
-#define LAST            0xf4
+#define M5REG          0xf8
+#define LAST            0xf8
 #define RESERVED        0xfc
 
 /* chip command register */

diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy
index ed95ce2336de3cd2068d7c08e3bd8cd257bd991b..7cc58421a455082289f193daf21874e221576578 100644 (file)
--- a/python/m5/objects/Ethernet.mpy
+++ b/python/m5/objects/Ethernet.mpy
@@ -72,6 +72,8 @@ simobj NSGigE(PciDevice):
     rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
     tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
 
+    m5reg = Param.UInt32(0, "Register for m5 usage")
+
     intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
     physmem = Param.PhysicalMemory(parent.any, "Physical Memory")