[i965] renable regative rhw test
authorZou Nan hai <nanhai.zou@intel.com>
Thu, 31 Jan 2008 10:22:19 +0000 (18:22 +0800)
committerZou Nan hai <nanhai.zou@intel.com>
Thu, 31 Jan 2008 10:22:19 +0000 (18:22 +0800)
src/mesa/drivers/dri/i965/brw_clip_line.c
src/mesa/drivers/dri/i965/brw_clip_tri.c
src/mesa/drivers/dri/i965/brw_vs_emit.c

index 7d51cddfc3d700d34b0b50212bf93d95ecfa9614..ab962562e5e660920ef4c5a3b992172b67a668ed 100644 (file)
@@ -148,12 +148,10 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    brw_clip_init_clipmask(c);
 
    /* -ve rhw workaround */
-   if (!BRW_IS_IGD(p->brw)) {
-      brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
-      brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
-              brw_imm_ud(1<<20));
-      brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
-   }
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
+                  brw_imm_ud(1<<20));
+   brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
 
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 
index f1fc6e1e9da875d47faa377cb70616ff375435ca..9d7b3def6675aacd3c22350a8037ec854004821a 100644 (file)
@@ -536,16 +536,14 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
 
    /* if -ve rhw workaround bit is set, 
       do cliptest */
-   if (!BRW_IS_IGD(p->brw)) {
-      brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
-      brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
-              brw_imm_ud(1<<20));
-      neg_rhw = brw_IF(p, BRW_EXECUTE_1); 
-      {
-         brw_clip_test(c);
-      }
-      brw_ENDIF(p, neg_rhw);
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
+                  brw_imm_ud(1<<20));
+   neg_rhw = brw_IF(p, BRW_EXECUTE_1); 
+   {
+          brw_clip_test(c);
    }
+   brw_ENDIF(p, neg_rhw);
    /* Can't push into do_clip_tri because with polygon (or quad)
     * flatshading, need to apply the flatshade here because we don't
     * respect the PV when converting to trifan for emit:
index 3cac97c71f46be9752363ab632db69138525d9bf..447e1182b30b1be283e7a7a3d66b9baf8fa23ae5 100644 (file)
@@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
        * Later, clipping will detect ucp[6] and ensure the primitive is
        * clipped against all fixed planes.
        */
-      if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) {
+      if (!c->key.know_w_is_one) {
         brw_CMP(p,
                 vec8(brw_null_reg()),
                 BRW_CONDITIONAL_L,