(no commit message)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 47303ea937b5be187ac8f40c1a803525c298e3d5..5c0ed23ef93be7cbe7cb8bd9fe74fbd686c565eb 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -81,10 +81,11 @@ The principle of SV is as follows:
 * A "Vector Length" CSR is set, indicating the span of any future
   "parallel" operations.
 * If any operation (a **scalar** standard RV opcode)
- uses a register that has been so "marked",
+ uses a register that has been so "marked"
+ ("tagged"),
  a hardware "macro-unrolling loop" is activated, of length
   VL, that effectively issues **multiple** identical instructions
-  using contiguous sequentially-incrementing register numbers.
+  using contiguous sequentially-incrementing register numbers, based on the "tags".
 * **Whether they be executed sequentially or in parallel or a
   mixture of both or punted to software-emulation in a trap handler
   is entirely up to the implementor**.