si_emit_compute_shader_pointers(sctx);
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
- sctx->atoms.s.render_cond.emit(sctx,
- &sctx->atoms.s.render_cond);
+ sctx->atoms.s.render_cond.emit(sctx);
si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
}
R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
-void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct si_atom *atom)
+void si_emit_graphics_shader_pointers(struct si_context *sctx)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;
RADEON_PRIO_QUERY);
}
-static void si_emit_query_predication(struct si_context *ctx,
- struct si_atom *atom)
+static void si_emit_query_predication(struct si_context *ctx)
{
struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
struct si_query_buffer *qbuf;
* CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
* if there is not enough PS outputs.
*/
-static void si_emit_cb_render_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_cb_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_blend *blend = sctx->queued.named.blend;
si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
}
-static void si_emit_blend_color(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_blend_color(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
pipe_resource_reference(&cb.buffer, NULL);
}
-static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_clip_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
}
-static void si_emit_clip_regs(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_clip_regs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *vs = si_get_vs_state(sctx);
/*
* infeered state between dsa and stencil ref
*/
-static void si_emit_stencil_ref(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_stencil_ref(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
}
-static void si_emit_db_render_state(struct si_context *sctx, struct si_atom *state)
+static void si_emit_db_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
}
}
-static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_framebuffer_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
sctx->framebuffer.dirty_zsbuf = false;
}
-static void si_emit_msaa_sample_locs(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_msaa_sample_locs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned nr_samples = sctx->framebuffer.nr_samples;
return true;
}
-static void si_emit_msaa_config(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_msaa_config(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
}
-static void si_emit_sample_mask(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_sample_mask(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned mask = sctx->sample_mask;
* command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
*/
struct si_atom {
- void (*emit)(struct si_context *ctx, struct si_atom *state);
+ void (*emit)(struct si_context *ctx);
};
struct si_state_blend {
void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
-void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct si_atom *atom);
+void si_emit_graphics_shader_pointers(struct si_context *sctx);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
bool old_perfect_enable);
/* si_state_binning.c */
-void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state);
+void si_emit_dpbb_state(struct si_context *sctx);
/* si_state_shaders.c */
bool si_update_shaders(struct si_context *sctx);
S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
}
-void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state)
+void si_emit_dpbb_state(struct si_context *sctx)
{
struct si_screen *sscreen = sctx->screen;
struct si_state_blend *blend = sctx->queued.named.blend;
{
/* Emit state atoms. */
unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
- while (mask) {
- struct si_atom *atom = &sctx->atoms.array[u_bit_scan(&mask)];
+ while (mask)
+ sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
- atom->emit(sctx, atom);
- }
sctx->dirty_atoms &= skip_atom_mask;
/* Emit states. */
/* <-- CUs are idle here. */
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
- sctx->atoms.s.render_cond.emit(sctx, NULL);
+ sctx->atoms.s.render_cond.emit(sctx);
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
return ps_input_cntl;
}
-static void si_emit_spi_map(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_spi_map(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *ps = sctx->ps_shader.current;
return true;
}
-static void si_emit_scratch_state(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_scratch_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_emit(cs, 4); /* poll interval */
}
-static void si_emit_streamout_begin(struct si_context *sctx, struct si_atom *atom)
+static void si_emit_streamout_begin(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_streamout_target **t = sctx->streamout.targets;
* are no buffers bound.
*/
-static void si_emit_streamout_enable(struct si_context *sctx,
- struct si_atom *atom)
+static void si_emit_streamout_enable(struct si_context *sctx)
{
radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(sctx->gfx_cs,
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
-static void si_emit_scissors(struct si_context *ctx, struct si_atom *atom)
+static void si_emit_scissors(struct si_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->gfx_cs;
struct pipe_scissor_state *states = ctx->scissors.states;
ctx->viewports.depth_range_dirty_mask = 0;
}
-static void si_emit_viewport_states(struct si_context *ctx,
- struct si_atom *atom)
+static void si_emit_viewport_states(struct si_context *ctx)
{
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);