#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
#define SYS_REG_INFO_HAS_BRAM (1ull << 2)
#define SYS_REG_BRAMINFO 0x10
+#define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull
#define SYS_REG_DRAMINFO 0x18
+#define SYS_REG_DRAMINFO_SIZE_MASK 0xfffffffffffffull
#define SYS_REG_CLKINFO 0x20
+#define SYS_REG_CLKINFO_FREQ_MASK 0xffffffffffull
#define SYS_REG_CTRL 0x28
#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
#define SYS_REG_CTRL_CORE_RESET (1ull << 1)
uint64_t proc_freq;
potato_uart_base = UART_BASE;
- proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO);
+ proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
}
printf("BRAM ");
printf("\n");
if (ftr & SYS_REG_INFO_HAS_BRAM) {
- val = readq(SYSCON_BASE + SYS_REG_BRAMINFO);
+ val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK;
printf(" BRAM: %lld KB\n", val / 1024);
}
if (ftr & SYS_REG_INFO_HAS_DRAM) {
- val = readq(SYSCON_BASE + SYS_REG_DRAMINFO);
+ val = readq(SYSCON_BASE + SYS_REG_DRAMINFO) & SYS_REG_DRAMINFO_SIZE_MASK;
printf(" DRAM: %lld MB\n", val / (1024 * 1024));
val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO);
printf(" DRAM INIT: %lld KB\n", val / 1024);
}
- val = readq(SYSCON_BASE + SYS_REG_CLKINFO);
+ val = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
printf(" CLK: %lld MHz\n", val / 1000000);
printf("\n");