return ''
def makeRead(self):
- return '%s = xc->readPC() + 4;\n' % self.base_name
+ return '%s = xc->readNextPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextPC(%s);\n' % self.base_name
return ''
def makeRead(self):
- return '%s = xc->readPC() + 8;\n' % self.base_name
+ return '%s = xc->readNextNPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextNPC(%s);\n' % self.base_name
format System {
0x2: cfc1({{
- std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
switch (FS)
}});
0x6: ctc1({{
- std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
-
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
uint32_t temp;
switch (FS)
format FloatOp {
0x1: cvt_d_s({{
- int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(,DOUBLE_TO_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
+ 0x4: cvt_w_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
+ 0x5: cvt_l_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
- 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
+ 0x6: cvt_ps_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/
+ }});
}
}
}
uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize);
return htog(result32);
+
case DoubleWidth:
uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize);
return NoFault;
}
+
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);