platforms/m1: resetless by default

diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index a096a38a26fa3bd70538886047231a46202d8079..d72a6bde1fd3528591c61efeaf522ead09c4f144 100644 (file)
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -119,7 +119,7 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
-                       lambda p: CRG_SE(p, "clk50", "user_btn"))
+                       lambda p: CRG_SE(p, "clk50", None))
 
        def do_finalize(self, fragment):
                try: