sim, arm: add checkpoint upgrader for d02b45a5

The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
obsoletes old checkpoints.

diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index e9de6f713aaf84020e55ba06b2000bb558ffb23a..888dba6149258c8ad793a734015f20cad98d2b6b 100644 (file)
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -59,7 +59,7 @@ class EventQueue;
  * SimObject shouldn't cause the version number to increase, only changes to
  * existing objects such as serializing/unserializing more state, changing sizes
  * of serialized arrays, etc. */
-static const uint64_t gem5CheckpointVersion = 0x000000000000000d;
+static const uint64_t gem5CheckpointVersion = 0x000000000000000e;
 
 template <class T>
 void paramOut(std::ostream &os, const std::string &name, const T &param);

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 66c67102549402d030d6b7bf00a1c8400c49adae..5d836a23d9026e62df03ca57fd26d810278ae884 100755 (executable)
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -602,6 +602,18 @@ def from_C(cpt):
                 cpt.set(sec, 'intRegs', ' '.join(intRegs))
                 cpt.set(sec, 'ccRegs',  ' '.join(ccRegs))
 
+# Checkpoint version E adds the ARM CONTEXTIDR_EL2 miscreg.
+def from_D(cpt):
+    if cpt.get('root','isa') == 'arm':
+        for sec in cpt.sections():
+            import re
+            # Search for all ISA sections
+            if re.search('.*sys.*\.cpu.*\.isa$', sec):
+                miscRegs = cpt.get(sec, 'miscRegs').split()
+                # CONTEXTIDR_EL2 defaults to 0b11111100000000000001
+                miscRegs[599:599] = [0xFC001]
+                cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs))
+
 migrations = []
 migrations.append(from_0)
 migrations.append(from_1)
@@ -616,6 +628,7 @@ migrations.append(from_9)
 migrations.append(from_A)
 migrations.append(from_B)
 migrations.append(from_C)
+migrations.append(from_D)
 
 verbose_print = False