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Added brackets for lha instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Tue, 26 Sep 2023 10:24:57 +0000 (11:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 29 Oct 2023 08:54:36 +0000 (08:54 +0000)
openpower/isa/fixedload.mdwn patch | blob | history

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index b63be01a461e8a5729f1107df1ac52e09b8b9e9c..14d728400ef87abd50d7a4ae5bf1569c716bbcb9 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -234,7 +234,7 @@ Description:
 
     Let the effective address (EA) be the sum (RA|0)+ D.
     The halfword in storage addressed by EA is loaded into
-    RT48:63. RT 0:47 are filled with a copy of bit 0 of the
+    RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
     loaded halfword.
 
 Special Registers Altered: