dvisampler/edid: fix sda sampling, needs to be similar to scl.

Video sources with high scl frequency were not able to access EDID information through I2C.
I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)

diff --git a/misoclib/video/dvisampler/edid.py b/misoclib/video/dvisampler/edid.py
index 16f18753e39ff101516ff983589038816ed6abc6..2a8e8b0828ee84cfcda36e9e64cf03bc773dd025 100644 (file)
--- a/misoclib/video/dvisampler/edid.py
+++ b/misoclib/video/dvisampler/edid.py
@@ -36,6 +36,7 @@ class EDID(Module, AutoCSR):
         # EDID
         scl_raw = Signal()
         sda_i = Signal()
+        sda_raw = Signal()
         sda_drv = Signal()
         _sda_drv_reg = Signal()
         _sda_i_async = Signal()
@@ -43,7 +44,7 @@ class EDID(Module, AutoCSR):
         self.specials += [
             MultiReg(pads.scl, scl_raw),
             Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
-            MultiReg(_sda_i_async, sda_i)
+            MultiReg(_sda_i_async, sda_raw)
         ]
 
         scl_i = Signal()
@@ -51,7 +52,10 @@ class EDID(Module, AutoCSR):
         samp_carry = Signal()
         self.sync += [
             Cat(samp_count, samp_carry).eq(samp_count + 1),
-            If(samp_carry, scl_i.eq(scl_raw))
+            If(samp_carry,
+                scl_i.eq(scl_raw),
+                sda_i.eq(sda_raw)
+            )
         ]
 
         scl_r = Signal()