re PR target/34932 ([avr] ICE in reload)

PR target/34932
* config/avr/avr.md (*addhi3_zero_extend2): Remove.

From-SVN: r135952

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eca37f97dc810f423812530d8ea188725d55996e..1dd372bb559319aedcf684b1ae51d20f72663d6b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2008-05-26  Andy Hutchinson  <hutchinsonandy@aim.com>
+
+       PR target/34932
+       * config/avr/avr.md (*addhi3_zero_extend2): Remove.
+
 2008-05-26  Richard Guenther  <rguenther@suse.de>
 
        * tree-ssa-sccvn.c (expr_has_constants): Declare.

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 137d3258833b38e845c42175f0208f50eaae8c57..47042e994367b4ffa93cb2ee7745971f7ac33ec9 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -587,18 +587,6 @@
   [(set_attr "length" "2")
    (set_attr "cc" "set_n")])
 
-(define_insn "*addhi3_zero_extend2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-       (plus:HI
-        (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
-        (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "add %0,%2
-       mov %B0,__zero_reg__
-       adc %B0,__zero_reg__"
-  [(set_attr "length" "3")
-   (set_attr "cc" "set_n")])
-
 (define_insn "*addhi3_sp_R_pc2"
   [(set (match_operand:HI 1 "stack_register_operand" "=q")
         (plus:HI (match_operand:HI 2 "stack_register_operand" "q")