x86: consolidate tracking of MMX register use

Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead
include the two special insns (not having register operands) explicitly.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b7d305f60c5b1aaf049d12f0cf73e155938f6e09..dba3faac802fb7d953a8dd4b0ffebe9795719305 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2019-12-04  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (output_insn): Don't consider Cpu* settings
+       when setting GNU_PROPERTY_X86_FEATURE_2_MMX.
+
 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 
        * testsuite/gas/i386/movdir.s: Add Intel syntax case with

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index b8babed68ba0b96c6df9530582f47f8a4dffe1af..b62af342684a7d29e73ac620e5256e74a1777777 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8259,15 +8259,9 @@ output_insn (void)
          || i.tm.cpu_flags.bitfield.cpu687
          || i.tm.cpu_flags.bitfield.cpufisttp)
        x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
-      /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
-        Xfence instructions.  */
-      if (i.tm.base_opcode != 0xf18
-         && i.tm.base_opcode != 0xf0d
-         && i.tm.base_opcode != 0xfaef8
-         && (i.has_regmmx
-             || i.tm.cpu_flags.bitfield.cpummx
-             || i.tm.cpu_flags.bitfield.cpua3dnow
-             || i.tm.cpu_flags.bitfield.cpua3dnowa))
+      if (i.has_regmmx
+         || i.tm.base_opcode == 0xf77 /* emms */
+         || i.tm.base_opcode == 0xf0e /* femms */)
        x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
       if (i.has_regxmm)
        x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;